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About

About

I received the Ph.D. degree in Electrical and  Computer Engineering from the University of Porto (Portugal) in 2001. I 'm currently an assistant professor with the Faculty of Engineering, University of Porto, and a senior researcher at INESC TEC. I'm a member of IEEE, ACM and Euromicro.


My research interests center around the design of dedicated digital systems for complex and demanding embedded applications. I'm particularly interested in three areas:

  • Design of self-adaptive digital systems
  • FPGA-based reconfigurable computing
  • Hardware acceleration of embedded systems
  • Some concrete research topics are:

    • dynamic reconfiguration of FPGAs
    • generation of FPGA configurations at run-time
    • fast physical synthesis for digital circuits
    • virtual programmable hardware architectures
    • transparent task migration from software→hardware

    Interest
    Topics
    Details

    Details

    • Name

      João Canas Ferreira
    • Role

      Senior Researcher
    • Since

      01st November 1988
    007
    Publications

    2024

    Memory Optimization for FPGA Implementation of Correlation-Based Beamforming

    Authors
    Avelar, H; Ferreira, JC;

    Publication
    2024 IEEE 22nd Mediterranean Electrotechnical Conference, MELECON 2024

    Abstract
    This paper proposes a method to avoid using a CORDIC or external memory to process the steering vectors to calculate the pseudospectrum of correlation-based beamforming algorithms. We show that if we decompose the steering vector equation, the size of the matrix to be saved in memory becomes independent of the antenna array size. Besides, the amount of data needed is small enough to be saved in the internal block RAMs of the FPGA SoC. Besides, this method greatly reduces the number of memory accesses, by offloading some processing to hardware, while keeping the frequency at 300MHz with a precision of 0.25°. Finally, we show that this approach is scalable since the complexity grows logarithmically for bigger arrays, and the symmetry in the matrices obtained allows even more compact data. © 2024 IEEE.

    2022

    A Flexible HLS Hoeffding Tree Implementation for Runtime Learning on FPGA

    Authors
    Sousa, LM; Paulino, N; Ferreira, JC; Bispo, J;

    Publication
    2022 IEEE 21ST MEDITERRANEAN ELECTROTECHNICAL CONFERENCE (IEEE MELECON 2022)

    Abstract
    Decision trees are often preferred when implementing Machine Learning in embedded systems for their simplicity and scalability. Hoeffding Trees are a type of Decision Trees that take advantage of the Hoeffding Bound to allow them to learn patterns in data without having to continuously store the data samples for future reprocessing. This makes them especially suitable for deployment on embedded devices. In this work we highlight the features of a HLS implementation of the Hoeffding Tree. The implementation parameters include the feature size of the samples (D), the number of output classes (K), and the maximum number of nodes to which the tree is allowed to grow (Nd). We target a Xilinx MPSoC ZCU102, and evaluate: the design's resource requirements and clock frequency for different numbers of classes and feature size, the execution time on several synthetic datasets of varying sizes (N) and the execution time and accuracy for two datasets from UCI. For a problem size of D=3, K=5, and N=40000, a single decision tree operating at 103MHz is capable of 8.3x faster inference than the 1.2 GHz ARM Cortex-A53 core. Compared to a reference implementation of the Hoeffding tree, we achieve comparable classification accuracy for the UCI datasets.

    2021

    Transparent Control Flow Transfer between CPU and Accelerators for HPC

    Authors
    Granhao, D; Ferreira, JC;

    Publication
    ELECTRONICS

    Abstract
    Heterogeneous platforms with FPGAs have started to be employed in the High-Performance Computing (HPC) field to improve performance and overall efficiency. These platforms allow the use of specialized hardware to accelerate software applications, but require the software to be adapted in what can be a prolonged and complex process. The main goal of this work is to describe and evaluate mechanisms that can transparently transfer the control flow between CPU and FPGA within the scope of HPC. Combining such a mechanism with transparent software profiling and accelerator configuration could lead to an automatic way of accelerating regular applications. In this work, a mechanism based on the ptrace system call is proposed, and its performance on the Intel Xeon+FPGA platform is evaluated. The feasibility of the proposed approach is demonstrated by a working prototype that performs the transparent control flow transfer of any function call to a matching hardware accelerator. This approach is more general than shared library interposition at the cost of a small time overhead in each accelerator use (about 1.3 ms in the prototype implementation).

    2021

    A Binary Translation Framework for Automated Hardware Generation

    Authors
    Paulino, N; Bispo, J; Ferreira, JC; Cardoso, JMP;

    Publication
    IEEE MICRO

    Abstract
    As applications move to the edge, efficiency in computing power and power/energy consumption is required. Heterogeneous computing promises to meet these requirements through application-specific hardware accelerators. Runtime adaptivity might be of paramount importance to realize the potential of hardware specialization, but further study is required on workload retargeting and offloading to reconfigurable hardware. This article presents our framework for the exploration of both offloading and hardware generation techniques. The framework is currently able to process instruction sequences from MicroBlaze, ARMv8, and riscv32imaf binaries, and to represent them as Control and Dataflow Graphs for transformation to implementations of hardware modules. We illustrate the framework's capabilities for identifying binary sequences for hardware translation with a set of 13 benchmarks.

    2021

    Pedagogical Innovation in Pandemic Times: The Experience of a Microprocessor Programming Course

    Authors
    Lima, B; Granhao, D; Araujo, AJ; Ferreira, JC;

    Publication
    2021 4TH INTERNATIONAL CONFERENCE OF THE PORTUGUESE SOCIETY FOR ENGINEERING EDUCATION (CISPEE)

    Abstract
    The 2019/2020 school year will always be remembered for the impact of the COVID-19 pandemic. For the first time in recent history, countries closed schools and forced instructors and students to quickly adjust to online classes. This sudden and forced shift to a method of teaching that was completely different from what we were used to presented several challenges and opportunities on a pedagogical level. In this paper we describe our experience as instructors in a course on microprocessor programming in the Master's Degree in Computer Science and Computing Engineering at the Faculty of Engineering of the University of Porto. Our approach included changes to the assessment plan, which became more distributed, and improvements in communication between students and instructors through the use of Slack. We found that the changes introduced were not only very well received by students, but also resulted in the best exam attendance and average final grade in the last 10 years of the course's history.

    Supervised
    thesis

    2023

    Design and evaluation of approximate arithmetic units for machine learning

    Author
    Miguel José Nunes Almeida

    Institution
    UP-FEUP

    2023

    Study and Implementation of Modular Software Architectures based on Hypervisors for Automotive Electronic Control Units

    Author
    Pedro Miguel Veiga de Almeida e Silva

    Institution
    UP-FEUP

    2023

    Real-time, Power-efficient Hardware acceleration of deep learning applications in Embedded Reconfigurable Devices for Advanced Driving Assistance Systems

    Author
    Amir Hossein Farzamiyan

    Institution
    UP-FEUP

    2023

    Implementation of Convolutional Neural Networks on a Versal Device

    Author
    Tiago David Sousa Ramos

    Institution
    UP-FEUP

    2023

    Simulation Infrastructure for Coupling CGRA Accelerator to RISC-V Processor

    Author
    António Francisco Rente Ribeiro

    Institution
    UP-FEUP