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About

Luis Miguel Pinho is Associate Professor at the Department of Computer Engineering - School of Engineering of the Polytechnic Institute of Porto (ISEP), being Director of the Master in Critical Computing Systems Engineering at ISEP. He has a PhD in Electrical and Computer Engineering (2001) and the Habilitation title in Informatics Engineering (2023) at the University of Porto.

Luis Miguel Pinho leads research in areas such as real-time and embedded software, programming languages, concurrency and parallelism, with a particular focus on the integration of high-performance computing with real-time embedded systems. 


He was responsible for several R&D projects, among which the FP7 R&D European Project P-SOCRATES, and coordinated activities in more than 25 projects, from fundamental research projects to industry funded technology transfer, including both single partner and in-consortia projects. He published more than 150 papers in international conferences and journals in the area of real-time, embedded and cyber-physical systems. He was General Chair of the Ada-Europe 2006 and ARCS 2015 conferences, Keynote Speaker at RTCSA 2010 and Program Co-Chair of Ada-Europe 2006, Ada-Europe 2012 and RTNS 2016. He was Editor-in-Chief of the Ada User Journal, from 2007 to 2019, and is currently Technical Editor of ACM Ada Letters. He is also a member of ISO/IEC JTC1/SC22/WG9 (Ada language), being one of the authors of the Ada 2022 parallel programing model.


Luis Miguel Pinho was Pro-President for Research and Innovation at the Polytechnic Institute of Porto from 2018 to 2022, and Executive Director of PORTIC (Porto Research, Technology & Innovation Center), Polytechnic's of Porto infrastructure for Research, Innovation and Entrepreneurship.

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Details

Details

  • Name

    Luis Miguel Pinho
  • Role

    Senior Researcher
  • Since

    14th December 2022
Publications

2023

A Scalable Clustered Architecture for Cyber-Physical Systems

Authors
Cabral, B; Costa, P; Fonseca, T; Ferreira, LL; Pinho, LM; Ribeiro, P;

Publication
2023 IEEE 21ST INTERNATIONAL CONFERENCE ON INDUSTRIAL INFORMATICS, INDIN

Abstract
Developing distributed and scalable Cyber-Physical Systems (CPS) that can handle large amounts of data at high data rates at the edge, remains a challenging task. Also, the limited availability of open-source solutions makes it difficult for developers and researchers to experiment with and deploy CPSs on a larger scale. This work introduces Edge4CPS, an open-source multi-architecture solution built over Kubernetes that aims to enable an easy to use, efficient and scalable solution for the deployment of applications on edge-like distributed computing clusters. To verify the successful real-world implementation of the introduced architecture, the system was tested in a railway scenario, derived from the Ferrovia 4.0 project, which highlights its functionalities.

2023

Framework for the Analysis and Configuration of Real-Time OpenMP Applications

Authors
Carvalho, T; Pinho, LM; Samadi, M; Royuela, S; Munera, A; Quiñones, E;

Publication
2023 IEEE 21ST INTERNATIONAL CONFERENCE ON INDUSTRIAL INFORMATICS, INDIN

Abstract
High-performance cyber-physical applications impose several requirements with respect to performance, functional correctness and non-functional aspects. Nowadays, the design of these systems usually follows a model-driven approach, where models generate executable applications, usually with an automated approach. As these applications might execute in different parallel environments, their behavior becomes very hard to predict, and making the verification of non-functional requirements complicated. In this regard, it is crucial to analyse and understand the impact that the mapping and scheduling of computation have on the real-time response of the applications. In fact, different strategies in these steps of the parallel orchestration may produce significantly different interference, leading to different timing behaviour. Tuning the application parameters and the system configuration proves to be one of the most fitting solutions. The design space can however be very cumbersome for a developer to test manually all combinations of application and system configurations. This paper presents a methodology and a toolset to profile, analyse, and configure the timing behaviour of highperformance cyber-physical applications and the target platforms. The methodology leverages on the possibility of generating a task dependency graph representing the parallel computation to evaluate, through measurements, different mapping configurations and select the one that minimizes response time.

2022

Configuration of Parallel Real-Time Applications on Multi-Core Processors

Authors
Gharajeh, MS; Carvalho, T; Pinho, LM;

Publication
2022 IEEE 20TH INTERNATIONAL CONFERENCE ON INDUSTRIAL INFORMATICS (INDIN)

Abstract
Parallel programming models (e.g., OpenMP) are more and more used to improve the performance of real-time applications in modern processors. Nevertheless, these processors have complex architectures, being very difficult to understand their timing behavior. The main challenge with most of existing works is that they apply static timing analysis for simpler models or measurement-based analysis using traditional platforms (e.g., single core) or considering only sequential algorithms. How to provide an efficient configuration for the allocation of the parallel program in the computing units of the processor is still an open challenge. This paper studies the problem of performing timing analysis on complex multi-core platforms, pointing out a methodology to understand the applications' timing behavior, and guide the configuration of the platform. As an example, the paper uses an OpenMP-based program of the Heat benchmark on a NVIDIA Jetson AGX Xavier. The main objectives are to analyze the execution time of OpenMP tasks, specify the best configuration of OpenMP directives, identify critical tasks, and discuss the predictability of the system/application. A Linux perf based measurement tool, which has been extended by our team, is applied to measure each task across multiple executions in terms of total CPU cycles, the number of cache accesses, and the number of cache misses at different cache levels, including L1, L2 and L3. The evaluation process is performed using the measurement of the performance metrics by our tool to study the predictability of the system/application.

2022

Heuristic-based Task-to-Thread Mapping in Multi-Core Processors

Authors
Gharajeh, MS; Royuela, S; Pinho, LM; Carvalho, T; Quinones, E;

Publication
2022 IEEE 27TH INTERNATIONAL CONFERENCE ON EMERGING TECHNOLOGIES AND FACTORY AUTOMATION (ETFA)

Abstract
OpenMP can be used in real-time applications to enhance system performance. However, predictability of OpenMP applications is still a challenge. This paper investigates heuristics for the mapping of OpenMP task graphs in underlying threads, for the development of time-predictable OpenMP programs. These approaches are based on a global scheduling queue, as well as per-thread allocation queues. The proposed method is divided into scheduling and allocation phases. In the former phase, OpenMP task-parts are discovered from OpenMP graph and placed in the scheduling queue. Afterwards, an appropriate allocation queue is selected for each task-part using four heuristic algorithms. In the latter phase, the best task-part is selected from the allocation queue to be allocated to and executed by an idle thread. Preliminary simulation results show that the new method overcomes BFS and WFS in terms of scheduling time and idle time.

2020

The AMPERE Project: A Model-driven development framework for highly Parallel and EneRgy-Efficient computation supporting multi-criteria optimization

Authors
Quinones, E; Royuela, S; Scordino, C; Gai, P; Pinho, LM; Nogueira, L; Rollo, J; Cucinotta, T; Biondi, A; Hamann, A; Ziegenbein, D; Saoud, H; Soulat, R; Forsberg, B; Benini, L; Mando, G; Rucher, L;

Publication
2020 IEEE 23RD INTERNATIONAL SYMPOSIUM ON REAL-TIME DISTRIBUTED COMPUTING (ISORC 2020)

Abstract
The high-performance requirements needed to implement the most advanced functionalities of current and future Cyber-Physical Systems (CPSs) are challenging the development processes of CPSs. On one side, CPSs rely on model-driven engineering (MDE) to satisfy the non-functional constraints and to ensure a smooth and safe integration of new features. On the other side, the use of complex parallel and heterogeneous embedded processor architectures becomes mandatory to cope with the performance requirements. In this regard, parallel programming models, such as OpenMP or CUDA, are a fundamental brick to fully exploit the performance capabilities of these architectures. However, parallel programming models are not compatible with current MDE approaches, creating a gap between the MDE used to develop CPSs and the parallel programming models supported by novel and future embedded platforms. The AMPERE project will bridge this gap by implementing a novel software architecture for the development of advanced CPSs. To do so, the proposed software architecture will be capable of capturing the definition of the components and communications described in the MDE framework, together with the non-functional properties, and transform it into key parallel constructs present in current parallel models, which may require extensions. These features will allow for making an efficient use of underlying parallel and heterogeneous architectures, while ensuring compliance with non-functional requirements, including those on real-time performance of the system.