Abstract
This work presents RVC (Reconfigurable Vector Coprocessor), a FPGA based custom computing machine for vector processing applications. This system was built to serve as an implementation platform for a custom vector processor designed for a digital signal processing application. Although its architecture has been in part dictated by the immediate needs of that dedicated processor, it also serves for other custom machines exhibiting similar requirements of vector processing. © 1998 IEEE.

Abstract

Abstract
In this paper we present a model based video coder for remote video surveillance applications at very low bit rates. Unlike the known model based video codecs, we use the model based approach for background modeling and not for "head-and-shoulders" modeling. Since in video surveillance the remote site that is being monitored is usually a previously known physically closed space, we build a 3-D model of the site and use it to synthesize the background of the scene for each of the video cameras used. The codec has two layers, one layer for the background using a 3-D model and a second layer for the part of the scene not represented by the background. The second layer may use conventional hybrid DPCM-DCT coding schemes, like H.263, or object-based coding techniques, like those used in MPEG-4 video VM. The proposed codec can be a good framework for a multiview codec.

Abstract
Mixed hardware/software applications may profit from the use of dynamically reconfigurable hardware for improved performance and adaptability. For this class of systems, the hardware, like the software, can be adapted during execution to the data being processed or to the reactions of the external system being controlled. This paper presents the prototype of an interactive system that supports the rapid development of such applications for a personal computer. The LISP-based prototype supports the assembly of hardware configurations in runtime by combination of component blocks from libraries; it also provides tools for partitioning computations described by a domain-independent data-flow model between software and hardware implementations. Whatever the implementation mode, computations are invoked in a uniform manner, making the dynamically reconfigurable hardware transparent to the user.

Abstract
The nesting (or placement) problem is an NP-hard combinatorial problem with important industrial applications, e.g. in apparel or footwear industry. This paper describes a hardware infrastructure to accelerate the processing of the underlying geometric information. The system consists of an FPGA-based reconfigurable platform enhanced by an ASIC for the processing of irregular polygons. The paper discusses the need for such a platform, establishes the main design guidelines and describes the architecture and modes of operation of both the reconfigurable infrastructure and the dedicated IC.

Abstract
We present a new algorithm for time-scale expansion of audio signals that comprises: time interpolation, frequency-scale expansion and modification of a spectral representation of the signal. The algorithm relies an an accurate model of signal analysis and synthesis, and was constrained to a non-iterative modification of the magnitudes and the wrapped phases of the relevant sinusoidal components of the signal. The structure of the algorithm is described and its performance is illustrated. A few examples of time-expanded wideband speech can be found on the Internet.