Abstract
Information systems depend on security mechanisms to detect and respond to cyber-attacks. One of the most frequent attacks is the Distributed Denial of Service (DDoS): it impairs the performance of systems and, in the worst case, leads to prolonged periods of downtime that prevent business processes from running normally. To detect this attack, several supervised Machine Learning (ML) algorithms have been developed and companies use them to protect their servers. A key stage in these algorithms is feature pre-processing, in which, input data features are assessed and selected to obtain the best results in the subsequent stages that are required to implement supervised ML algorithms. In this article, an innovative approach for feature selection is proposed: the use of Visibility Graphs (VGs) to select features for supervised machine learning algorithms used to detect distributed DoS attacks. The results show that VG can be quickly implemented and can compete with other methods to select ML features, as they require low computational resources and they offer satisfactory results, at least in our example based on the early detection of distributed DoS. The size of the processed data appears as the main implementation constraint for this novel feature selection method.

Abstract
In an era marked by escalating cyber threats, the need for robust cybersecurity measures is paramount, especially for Higher Education Institutions (HEIs). As custodians of sensitive information, HEIs must ensure secure channels for data transmission to protect their stakeholders. These institutions should increase their cyber resilience, recognizing the heightened risk they face from cybercriminal activities. A breach in an HEI’s cybersecurity can have severe consequences, ranging from data confidentiality breaches to operational disruptions and damage to institutional reputation. This paper conducts a comprehensive evaluation of the cybersecurity mechanisms in HEIs within Poland. The focus is on assessing the adoption of important web security protocols—Hyper Text Transfer Protocol Secure (HTTPS) and Domain Name System Security Extensions (DNSSEC)—and the implementation of security headers on HEI websites. This study aims to provide a snapshot of the current cyber defense maturity in HEIs and to offer actionable insights for enhancing web security practices. The findings indicate a high adoption rate of HTTPS among HEIs, yet reveal significant gaps in web security practices. Also, there is a low adherence to security headers and an absence regarding DNSSEC implementation across the surveyed institutions. These results highlight crucial areas for improvement and underscore the need for HEIs in Poland to strengthen their web security measures, safeguarding their data and enhancing the overall cybersecurity resilience. © 2024 by SCITEPRESS – Science and Technology Publications, Lda.

Abstract
This paper provides an overview of the SUPERIOT project, an EU SNS JU (Smart Networks and Services Joint Undertaking) initiative focused on developing truly sustainable IoT systems. The SUPERIOT concept is based on a unique holistic approach to sustainability, proactively developing sustainable solutions considering the design, implementation, usage and disposal/reuse stages. The concept exploits radio and optical technologies to provide dual-mode wireless connectivity and dual-mode energy harvesting as well as dual-mode IoT node positioning. The implementation of the IoT nodes or devices will maximize the use of sustainable printed electronics technologies, including printed components, conductive inks and substrates. The paper describes the SUPERIOT concept, covering the key technical approaches to be used, promising scenarios and applications, project goals and demonstrators which will be developed to the proof-of-concept stage. In addition, the paper briefly discusses some important visions on how this technology may be further developed in the future.

Abstract
Despite the trend towards ubiquitous wireless connectivity, there are scenarios where the communications infrastructure is damaged and wireless coverage is insufficient or does not exist, such as in natural disasters and temporary crowded events. Flying networks, composed of Unmanned Aerial Vehicles (UAV), have emerged as a flexible and cost-effective solution to provide on-demand wireless connectivity in these scenarios. UAVs have the capability to operate virtually everywhere, and the growing payload capacity makes them suitable platforms to carry wireless communications hardware. The state of the art in the field of flying networks is mainly focused on the optimal positioning of the flying nodes, while the wireless link parameters are configured with default values. On the other hand, current link adaptation algorithms are mainly targeting fixed or low mobility scenarios. We propose a novel rate adaptation approach for flying networks, named Trajectory Aware Rate Adaptation (TARA), which leverages the knowledge of flying nodes’ movement to predict future channel conditions and perform rate adaptation accordingly. Simulation results of 100 different trajectories show that our solution increases throughput by up to 53% and achieves an average improvement of 14%, when compared with conventional rate adaptation algorithms such as Minstrel-HT. © ICST Institute for Computer Sciences, Social Informatics and Telecommunications Engineering 2024.

Abstract
This work addresses the contemporary challenges in computing, caused by the stagnation of Moore's Law and Dennard scaling. The shift towards heterogeneous architectures necessitates innovative compilation strategies, prompting initiatives like the Multi-Level Intermediate Representation (MLIR) project, where progressive code lowering can be achieved through the use of dialects. Our work focuses on developing an MLIR dialect capable of representing streaming data accesses to memory, and Single Instruction Multiple Data (SIMD) vector operations. We also propose our own Structured Representation Language (SRL), a Design Specific Language (DSL) to serve as a precursor into the MLIR layer and subsequent inter-operation between new and existing dialects. The SRL exposes the streaming and vector computational concepts to a higher-level, and serves as intermediate step to supporting code generation containing our proposed dialect from arbitrary input code, which we leave as future work. This paper presents the syntaxes of the SRL DSL and of the dialect, and illustrates how we aim to employ them to target both General-Purpose Processors (GPPs) with SIMD co-processors and custom hardware options such as Field-Programmable Gate Arrayss (FPGAs) and Coarse-Grained Re-configurable Arrays (CGRAs).

Abstract
Hardware specialization is seen as a promising venue for improving computing efficiency, with reconfigurable devices as excellent deployment platforms for application-specific architectures. One approach to hardware specialization is via the popular RISC-V, where Instruction Set Architecture (ISA) extensions for domains such as Edge Artifical Intelligence (AI) are already appearing. However, to use the custom instructions while maintaining a high (e.g., C/C++) abstraction level, the assembler and compiler must be modified. Alternatively, inline assembly can be manually introduced by a software developer with expert knowledge of the hardware modifications in the RISC-V core. In this paper, we consider a RISC-V core with a vectorization and streaming engine to support the Unlimited Vector Extension (UVE), and propose an approach to automatically transform annotated C loops into UVE compatible code, via automatic insertion of inline assembly. We rely on a source-to-source transformation tool, Clava, to perform sophisticated code analysis and transformations via scripts. We use pragmas to identify code sections amenable for vectorization and/or streaming, and use Clava to automatically insert inline UVE instructions, avoiding extensive modifications of existing compiler projects. We produce UVE binaries which are functionally correct, when compared to handwritten versions with inline assembly, and achieve equal and sometimes improved number of executed instructions, for a set of six benchmarks from the Polybench suite. These initial results are evidence towards that this kind of translation is feasible, and we consider that it is possible in future work to target more complex transformations or other ISA extensions, accelerating the adoption of hardware/software co-design flows for generic application cases.