Abstract
Introduction: Previous studies have shown that adverse childhood experiences negatively impact child development, with consequences throughout the lifespan. Some of these consequences include the exacerbation or onset of several pathologies and risk behaviors. Materials and Methods: A convenience sample of 398 individuals aged 20 years or older from the Porto metropolitan area, with quotas, was collected. The evaluation was conducted using an anonymous questionnaire that included sociodemographic questions about exposure to adverse childhood experiences, a list of current health conditions, questions about risk behaviors, the AUDIT-C test, the Fagerstrom test and the Childhood Trauma Questionnaire-brief form. Variables were quantified to measure adverse childhood experiences, pathologies, and risk behaviors in adult individuals for comparison purposes. Results: Individuals with different forms of adverse childhood experiences present higher rates of smoking dependence, self-harm behaviors, victimization of/aggression toward intimate partners, early onset of sexual life, sexually transmitted infections, multiple sexual partners, abortions, anxiety, depression, diabetes, arthritis, high cholesterol, hypertension, and stroke. Different associations are analyzed and presented. Discussion and Conclusions: The results show that individuals with adverse childhood experiences have higher total scores for more risk behaviors and health conditions than individuals without traumatic backgrounds. These results are relevant for health purposes and indicate the need for further research to promote preventive and protective measures.

Abstract
The FotoInMotion (FiM) project is building a novel media creation platform, leveraging the use of semi-automated analysis and editing tools to empower creators to easily transform static visual acquisitions of real-world events into rich, animated and engaging objects, distributable through common channels. FiM transforms the content creative chain into an integrated pipeline across which media and metadata seamlessly flow and are exploited to produce more complex media objects. One of the addressed challenges consists the need for a seamless and efficient communication across such pipeline and on how to preserve, in a structured manner, all of the involved media and metadata. Existing standardized metadata tools and content wrappers are limited in expressivity and scope and incapable of fully supporting the needs of the content creative pipeline. This paper describes FiM's new structured data object, i.e. the Digital Event (DE), which acts as a universal vehicle for media and metadata. It builds on well-established and emergent MPEG standards (MPEG-21, MPEG-V, MPEG-7 and MPEG HEIF), to support data diversity, interoperability, packaging and sharing, within complex, Machine Learning enhanced, creative pipelines. Our solution has been validated by creative professionals (photojournalism, fashion marketing and festivals), who have conducted experiments within the context of different creative workflows in real world scenarios. DE's employment revealed to be advantageous, particularly in the homogenization of the media and metadata representation and packaging and in the normalization of the interaction between different pipeline components.

Abstract
Heterogeneous platforms with FPGAs have started to be employed in the High-Performance Computing (HPC) field to improve performance and overall efficiency. These platforms allow the use of specialized hardware to accelerate software applications, but require the software to be adapted in what can be a prolonged and complex process. The main goal of this work is to describe and evaluate mechanisms that can transparently transfer the control flow between CPU and FPGA within the scope of HPC. Combining such a mechanism with transparent software profiling and accelerator configuration could lead to an automatic way of accelerating regular applications. In this work, a mechanism based on the ptrace system call is proposed, and its performance on the Intel Xeon+FPGA platform is evaluated. The feasibility of the proposed approach is demonstrated by a working prototype that performs the transparent control flow transfer of any function call to a matching hardware accelerator. This approach is more general than shared library interposition at the cost of a small time overhead in each accelerator use (about 1.3 ms in the prototype implementation).

Abstract
As applications move to the edge, efficiency in computing power and power/energy consumption is required. Heterogeneous computing promises to meet these requirements through application-specific hardware accelerators. Runtime adaptivity might be of paramount importance to realize the potential of hardware specialization, but further study is required on workload retargeting and offloading to reconfigurable hardware. This article presents our framework for the exploration of both offloading and hardware generation techniques. The framework is currently able to process instruction sequences from MicroBlaze, ARMv8, and riscv32imaf binaries, and to represent them as Control and Dataflow Graphs for transformation to implementations of hardware modules. We illustrate the framework's capabilities for identifying binary sequences for hardware translation with a set of 13 benchmarks.

Abstract
The 2019/2020 school year will always be remembered for the impact of the COVID-19 pandemic. For the first time in recent history, countries closed schools and forced instructors and students to quickly adjust to online classes. This sudden and forced shift to a method of teaching that was completely different from what we were used to presented several challenges and opportunities on a pedagogical level. In this paper we describe our experience as instructors in a course on microprocessor programming in the Master's Degree in Computer Science and Computing Engineering at the Faculty of Engineering of the University of Porto. Our approach included changes to the assessment plan, which became more distributed, and improvements in communication between students and instructors through the use of Slack. We found that the changes introduced were not only very well received by students, but also resulted in the best exam attendance and average final grade in the last 10 years of the course's history.

Abstract
By using Dynamic Binary Translation, instruction traces from pre-compiled applications can be offloaded, at runtime, to FPGA-based accelerators, such as Coarse-Grained Loop Accelerators, in a transparent way. However, scheduling onto coarse-grain accelerators is challenging, with two of current known issues being the density of computations that can be mapped, and the effects of memory accesses on performance. Using an in-house framework for analysis of instruction traces, we explore the effect of different window sizes when applying list scheduling, to map the window operations to a coarse-grain loop accelerator model that has been previously experimentally validated. For all window sizes, we vary the number of ALUs and memory ports available in the model, and comment how these parameters affect the resulting latency. For a set of benchmarks taken from the PolyBench suite, compiled for the 32-bit MicroBlaze softcore, we have achieved an average iteration speedup of 5.10x for a basic block repeated 5 times and scheduled with 8 ALUs and memory ports, and an average speedup of 5.46x when not considering resource constraints. We also identify which benchmarks contribute to the difference between these two speedups, and breakdown their limiting factors. Finally, we reflect on the impact memory dependencies have on scheduling.