Abstract
This paper presents analog building blocks that find potential applications in display panels. A buffer (source-follower), subtractor, adder, and high-gain amplifier, employing only n-type enhancement amorphous gallium-indium-zinc-oxide thin-film transistors (a-GIZO TFTs), were designed, simulated, fabricated, and characterized. Circuit simulations were carried out using a neural model developed in-house from the measured characteristics of the transistors. The adder-subtractor circuit presents a power consumption of 0.26 mW, and the amplifier presents a gain of 34 dB and a power consumption of 0.576 mW, with a load of 10 M Omega//16 pF. To the authors' knowledge, this is the highest gain reported so far for a single-stage amplifier with a-GIZO TFT technology.

Abstract
Sparse coding techniques have seen an increasing range of applications in recent years, especially in the area of image processing. In particular, sparse coding using l1-regularization has been efficiently solved with the Augmented Lagrangian (AL) applied to its dual formulation (DALM). This paper proposes the decomposition of the dictionary matrix in its Singular Value/Vector form in order to simplify and speed-up the implementation of the DALM algorithm. Furthermore, we propose an update rule for the penalty parameter used in AL methods that improves the convergence rate. The SVD of the dictionary matrix is done as a pre-processing step prior to the sparse coding, and thus the method is better suited for applications where the same dictionary is reused for several sparse recovery steps, such as block image processing. © 2014 IEEE.

Abstract
This paper presents a novel low-power analog circuit, with n-type IGZO TFTs that can function as an adder operator or be designed to operate as a driver. Experiments were set to show summation of up to four signals. However, the design can easily be expanded to add higher number of signals, by appending a single TFT at the input per each additional signal. The circuit is simple, uses a single power supply irrespective to the number of input voltage signals, and shows good accuracy over a reasonable range of input values. By choosing proper TFT dimensions, the topology can replace the typical output drivers of TFT amplifiers, namely the common-drain with current source biasing, or the common-source with diode connected load. The circuit was fabricated with a temperature that does not exceeds 200 degrees C. Its performance is characterized from measurements at room temperature and normal ambient, with a power supply voltage of 12 V and a load of approximate to 4 pF. The proposed circuit has shown a linearity error less than 3.2% (up to an input signal peak-to-peak value of 2 V), a power consumption of 78 mu W and a bandwidth of approximate to 115 kHz, under worst case condition (when it is adding four signals with the same frequency). It has shown superior performance in terms of linearity when compared to the typical drivers considered in this study. In addition, it has shown almost the same behavior when measurements were repeated after one year. Therefore, the proposed circuit is a robust viable alternative to conventional approaches, being more compact, and contributes to increase the functionality of large-area flexible electronics.

Abstract
A high-gain amplifier topology, with all single n-type enhancement transistors, is proposed in this paper. This type of circuits are essential in transparent TFT technologies, such as GIZO and ZnO that lack complementary type transistor. All circuits were simulated using BSIM3V3 model of a 0.35 mu m CMOS technology, due to the absence of a complete electrical model for the TFTs. Results reveal that the proposed circuit promise more gain, lower power consumption and higher bandwidth than the existing solutions under identical bias conditions.

Abstract
An integrate-and-fire modulator (IFM) is designed for power scavenging systems like: Wireless Sensor Network (WSN) and Radio Frequency Identification (RFID) sensor tags. The circuit works with a clock in order to be able to be synchronized with microprocessors, which must be used to reconstruct the signal. The modulator is simulated using 130nm CMOS technology and the resulting power consumption is around 14nW at a clock frequency of 10 kHz. The OTA individually dissipates roughly 13nW. Signal reconstruction resulted in a 9.2 ENOB.

Abstract
This paper presents a behavioral model for amorphous indium-gallium-zinc oxide thin-film transistor using artificial neural network (ANN) based equivalent circuit (EC) approach to predict static and dynamic behavior of the device. In addition, TFT parasitic capacitances (C-GS and C-GD) characterization through measurements is also reported. In the proposed model, an EC is derived from the device structure, in terms of electrical lumped elements. Each electrical element in the EC is modeled with an ANN. Then these ANNs are connected together as per the EC and implemented in Verilog-A. The proposed model performance is validated by comparing the circuit simulation results with the measured response of a simple common-source amplifier, which has shown 12.2 dB gain, 50 mu W power consumption and 85 kHz 3-dB frequency with a power supply of 6 V. The same circuit is tested as an inverter and its response is also presented up to 50 kHz, from both simulations and measurements. These results show that the model is capable of capturing both small and large signal behavior of the device to good accuracy, even including the harmonic distortion of the signal (that emphasizes the nonlinear behavior of the parasitic capacitance), making the model suitable for IC design.