Abstract
IEEE 1149.1, commonly known as the joint test action group (JTAG), is the standard for the test access port and the boundary-scan architecture. The JTAG is primarily utilized at the time of the integrated circuit (IC) manufacture but also in the field, giving access to internal sub-systems of the IC, or for failure analysis and debugging. Because the JTAG needs to be left intact and operational for use, it inevitably provides a "backdoor" that can be exploited to undermine the security of the chip. Potential attackers can then use the JTAG to dump critical data or reverse engineer IP cores, for example. Since an attacker will use the JTAG differently from a legitimate user, it is possible to detect the difference using machine-learning algorithms. A JTAG protection scheme, SLIC-J, is proposed to monitor user behavior and detect illegitimate accesses to the JTAG. Specifically, JTAG access is characterized using a set of specifically-defined features, and then an on-chip classifier is used to predict whether the user is legitimate or not. To validate the effectiveness of the approach, both legitimate and illegitimate JTAG accesses are simulated using the OpenSPARC T2 benchmark. The results show that the detection accuracy is 99.2%, and the escape rate is 0.8%.

Abstract
This paper presents a network router and transceiver for wearable, low-power, high-speed Body Area Networks (BAN) applications running in a mesh network of sensors embedded in textiles and connected to each other with conductive yarns functioning as bidirectional transmission channels. The routing of data packets from sensor nodes to a sink node is based on hybrid circuit and packet switching. In comparison with pure packet switching, hybrid routing decreases end-to-end delay, power consumption and buffer size. The proposed design uses independent sender, receiver and circuit switching modules, thereby allowing the nodes to simultaneously send and receive data. The simulation results show that circuit and hybrid switching modes significantly increase the performance of the system. In addition, implementing the complete packet process on FPGA, instead of using an external microcontroller as in previous work, enables a much faster routing process. The results are based on a Verilog description of the system, which has been synthesized for a low-power IGLOO FPGA with Libero Project Manager and simulated with ModelSim. The implementation operates successfully at a data rate of 20 Mbps.

Abstract
This paper presents a new methodology to maximize the power output of Photovoltaic panels (PV), based on an adaptive duty-cycle methodology. The approach embeds the DC/DC converter characteristic in the cost function, allowing an optimization based on a single measured variable. Two cost functions, and respective learning rules, are derived. The first, more complex and comprehensive, traces the ground for the second which is less computational intensive and solves stability issues and implementation difficulties. It is also demonstrated that the system is asymptotically stable around the optimum duty-cycle, in the Lyapunov sense. Both methods are compared through simulations and deviations from the optimal solution are assessed.

Abstract
This article presents European-based contributions for wireless power transmission (WPT), related to applications ranging from future Internet of Things (IoT) and fifth-generation (5G) systems to high-power electric vehicle charging. The contributors are all members of a European consortium on WPT, COST Action IC1301. WPT is the driving technology that will enable the next stage in the current consumer electronics revolution, including batteryless sensors, passive RF identification (RFID), passive wireless sensors, the IoT, and machine-to-machine solutions. The article discusses the latest developments in research by some of the members of this group.

Abstract
This paper presents a low-power binary phase shift keying (BPSK) pulse generator for ultra-wide-band transmitters. The circuit has been designed based on LC-tank resonators using 0.13 um CMOS technology. Simulation shows -10dB bandwidth of around 3 GHz and power consumption of 2 mW at 100 MHz PRF. Peak-peak amplitude voltage for both symbols '1' and '0' are approximately as large as 1.2V supply voltage and can radiate enough energy to satisfy the FCC mask only by one pulse. Thus, the energy consumption is 20 pJ/pulse/bit. Pulse duration is 1.5 ns and the transmitter can reach data rates of 660 Mbps

Abstract
This paper presents the characterization of fundamental analog and digital circuits with a-IGZO TFTs from measurements performed at normal ambient. The fundamental blocks considered in this work include digital logic gates, a low power single stage high-gain amplifier with capcacitive bootstrapping and a level shifter/buffer. These circuits are important functional blocks in analog/Mixed signal IC design with oxide TFTs. Being fabricated at low temperature (<200 degrees C), they can find potential applications in low-cost large-area flexible systems.