Abstract
This paper presents and evaluates a high-precision, one-way, and master-to-slave time synchronization protocol to minimize the clock time skew in low-power wearable sensor networks. The protocol is implemented in the media access control layer, and is based on directly eliminating deterministic delays during transmission from source to destination node, at hardware level. The proposed protocol keeps the one-hop average synchronization error close to the signal propagation delay, and the one-hop peak-to-peak jitter equals to the period of each node's system clock period. Both values grow linearly as the hop count increases. The protocol can achieve synchronization in the range of a few nanoseconds, enough to satisfy the requirements of many applications related to wearable networks, with one-way messages. Both theoretical analysis and experimental results, in wired wearable networks, show that the proposed protocol has a better performance than precision time protocol and a standard timing protocol for both single and multi-hop situations. The proposed approach is simpler, requires no calculations, and exchanges fewer messages. Experimental results obtained with an implementation of the protocol in a 0.35-mu m CMOS technology show that this approach keeps the one-hop average clock skew around 4.6 ns and peak-to-peak skew around 50 ns for a system clock frequency of 20 mh.

Abstract
Development time and accuracy are measures that need to be taken into account when devising device models for a new technology. If complex circuits need to be designed immediately, then it is very important to reduce the time taken to realize the model. Solely based on data measurements, artificial neural networks (ANNs) modeling methodologies are capable of capturing small and large signal behavior of the transistor, with good accuracy, thus becoming excellent alternatives to more strenuous modeling approaches, such as physical and semi-empirical. This paper then addresses a static modeling methodology for amorphous Gallium-Indium-Zinc-Oxide - Thin Film Transistor (a-GIZO TFT), with different ANNs, namely: multilayer perceptron (MLP), radial basis functions (RBF) and least squares-support vector machine (LS-SVM). The modeling performance is validated by comparing the model outcome with measured data extracted from a real device. In case of a single transistor modeling and under the same training conditions, all the ANN approaches revealed a very good level of accuracy for large- and small-signal parameters (g(m) and g(d)), both in linear and saturation regions. However, in comparison to RBF and LS-SVM, the MLP achieves a very acceptable degree of accuracy with lesser complexity. The impact on simulation time is strongly related with model complexity, revealing that MLP is the most suitable approach for circuit simulations among the three ANNs. Accordingly, MLP is then extended for multiple TFTs with different aspect ratios and the network implemented in Verilog-A to be used with electric simulators. Further, a simple circuit (inverter) is simulated from the developed model and then the simulation outcome is validated with the fabricated circuit response.

Abstract
The work reported in this paper introduces a periodic switching technique applied to continuous-time filters, whose outcome is an equivalent filter with scaled time-constants. The principle behind the method is based on a procedure that extends the integration time by periodically interrupting the normal integration of the filter. The net result is an up scaling of the time constant, inversely proportional to the switching duty-cycle. This is particularly suitable for reducing the area occupied by passive devices in integrated circuits, as well as to accurately calibrate the filter dynamics. Previous works have been following this concept in an entirely continuous-time perspective, either focusing on specific circuits or using approximations to provide an extended analysis. This paper includes input/output sampling to derive a closed-form representation for the scaling technique herein coined as 'Filter & Hold' (F&H). A detailed mathematical analysis is described, demonstrating that the F&H concept represents an exact filtering solution. Simulation results and experimental measurements are provided to further validate the theoretical analysis for an F&H vector-filter prototype. Copyright (C) 2014 John Wiley & Sons, Ltd.

Abstract
This paper presents a planar antenna using low temperature co-fired ceramics (LTCC) substrate for extreme environment applications. An ultra wideband (UWB) elliptical patch antenna was designed and fabricated using an LTCC Ceramtec GC substrate to demonstrate the capabilities of the technology for wideband applications. The simulated results were further validated experimentally. The fabricated antenna provides a peak gain of 5dB over a bandwidth of 4 GHz (3 GHz 7 GHz) with return loss better than -10dB. The radiation pattern is omni-directional in the horizontal plane (theta=90 degrees) over the whole frequency range.

Abstract
Human motion capture systems help clinicians to detect and identify mobility impairments, early stages of pathologies and evaluate the effectiveness of surgical or rehabilitation intervention. Although there is a considerable number of solutions presently available, these systems are often expensive, complex, difficult to wear, and uncomfortable for the patient. With the purpose of solving the formerly mentioned problems, a new wearable locomotion data capture system for gait analysis is being developed. This system will allow the measurement of several locomotion-related parameters in a practical and non-invasive way, also reusable, that can be used by patients from light to severe impairments or disabilities. © 2013 The Textile Machinery Society of Japan.

Abstract
Transparent TFT technologies, with amorphous semiconductor oxides are lacking a complementary type transistor. This represents a real challenge, when the design of high-gain amplifiers are considered, without resorting to passive resistive elements. However, some solutions do exist to overcome the lack of a p-type transistor. This paper then presents a comparison analysis of two high-gain single-stage amplifier topologies using only n-type enhancement transistors. In these circuits, high gain is achieved using positive feedback for the load impedance. The comparison is carried out in terms of bandwidth, power consumption and complexity under identical bias conditions. Further, the same load impedance is used to develop a novel high-gain multiplier. All the circuits are simulated using a 0.35 mu m CMOS technology, as it is easy to test the reliability of the methods, since CMOS transistors have trustworthy models.