Abstract
Reconfigurable computing has already confirmed a significant potential for accelerating certain computing tasks. However, the most successful applications relied on user expertise to design a specific architecture implemented by the hardware structures of the reconfigurable computing device. Hence, one of the most challenging issues is to map, efficiently and automatically, computations (described in software programming languages) to reconfigurable computing devices. This paper presents CHIADO, a research project aiming a compiler framework to map efficiently software programs to reconfigurable computing platforms, especially the ones based on FPGA (Field-Programmable Gate Array) devices. The framework is also intended to support research of new optimization techniques. The project, based on our previous work on compiling Java bytecodes to FPGAs, focuses on high-performance solutions, schemes to estimate the impact of some transformations supported by the compiler (partial/full loop unrolling), and schemes to take advantage of dynamic reconfiguration (e.g., temporal partitioning). This paper gives an overview about the CHIADO project, shows the framework, and enumerates the main project goals.

Abstract
The von Neumann-style architectures have been tremendously well succeeded by taking advantage of the Moore's law. It is now understood that, it will be very difficult to meet the supercomputing demands of the future computing systems with this style of microprocessor architectures. Most nowadays applications require high-performance for processing data streams. Being dataflow computing a natural paradigm to process data streams, architectures based on dataflow principles are emerging as a way to meet the supercomputing demands. Data-driven arrays, introduced in the 80's, are examples of such architectures. They devised a scalable and effective fashion to directly support the dataflow model of computation and have been revived by a number of reconfigurable architectures (e.g., KressArray, WaveScalar, and XPP). Those coarse-grained reconfigurable architectures with dataflow semantics depict interesting achievements with respect to performance and programming methodologies, when compared to other computing platforms. This paper presents the most interesting data-driven array architectures. Trends and open issues related to a number of properties at architectural level and to compilation techniques are enumerated and discussed. A number of features are illustrated, especially the support for hardware virtualization, speculative configuration, and software pipelining. Examples using the PACT XPP reconfigurable array are shown. Those examples include the ADPCM decoder, from the MediaBench repository, and LeeDCT, an optimized DCT algorithm.

Abstract

Abstract

Abstract
This paper presents an infrastructure to verify the functionality of the specific architectures generated by a high-level compiler, targeting dynamically reconfigurable hardware. Java, XML, and XSL technologies are used to support the infrastructure. As simulation engine we use Hades, an event driven Java based simulator. It results in a suitable scheme to test the designs generated by the compiler each time a new optimization technique is included or changes in the compiler are performed. We believe this infrastructure will be very important to verify, by functional simulation, further research techniques, as far as compilation to FPGA-based reconfigurable computing is concerned.

Abstract
Sequences of loops or sets of nested loops exist in many applications. This paper shows a scheme to pipeline those sequences of loops in such a way that subsequent loops can start execution before the end of the previous ones. It uses a hardware scheme with decoupled and concurrent datapath and control units that start execution at the same time. The communication of data items between two loops in sequence is conducted by memories. Each element of one of such memories is responsible to flag the availability of the data requested by a subsequence loop. Thus, the control execution of subsequent loops is also orchestrated by data availability and out-of-order produced-consumed pairs are permitted. We apply the concept to a real example: a fast DCT algorithm.