Abstract
The development of applications for high-performance embedded systems is typically a long and error-prone process. In addition to the required functions, developers must consider various and often conflicting non-functional application requirements such as performance and energy efficiency. The complexity of this process is exacerbated by the multitude of target architectures and the associated retargetable mapping tools. This paper introduces an Aspect-Oriented Programming (AOP) approach that conveys domain knowledge and non-functional requirements to optimizers and mapping tools. We describe a novel AOP language, LARA, which allows the specification of compilation strategies to enable efficient generation of software code and hardware cores for alternative target architectures. We illustrate the use of LARA for code instrumentation and analysis, and for guiding the application of compiler and hardware synthesis optimizations. An important LARA feature is its capability to deal with different join points, action models, and attributes, and to generate an aspect intermediate representation. We present examples of our aspect-oriented hardware/software design flow for mapping real-life application codes to embedded platforms based on Field Programmable Gate Array (FPGA) technology. © 2012 ACM.

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Abstract
This paper presents an approach to teaching design of non-programmable application-specific architectures using VHDL, logic and physical synthesis tools and FPGAs. The approach relies on mini-projects that resemble typical problems that students may face in real-life concerning the design of application-specific architectures. The teaching approach presented in this paper supports the incremental learning of both VHDL and the tools used. as the projects are being developed, i.e., students are motivated to acquire skills at the pace at which those skills are required to advance project development. The results so far are very encouraging. Even students with little knowledge of hardware design and embedded systems have succeeded in their assignments. Feedback obtained front students reveals the suitability of certain aspects of the approach and the major difficulties they have faced.

Abstract
This paper presents an offline tool-chain which automatically extracts loops (Mega blocks) from Micro Blaze instruction traces and creates a tailored Reconfigurable Processing Unit (RPU) for those loops. The system moves loops from the CPU to the RPU transparently, at runtime, and without changing the executable binaries. The system was implemented in an FPGA and for the tested kernels measured speedups ranged between 3.9x and 18.2x for a Micro Blaze CPU without cache. We estimate speedups from 1.03x to 2.01x, when comparing to the best estimated performance achieved with a single Micro Blaze. © 2011 IEEE.

Abstract
Meeting safety requirements typically require substantial invasive extensions to applications. Even in the absence of faults, the overhead associated with these invasive extensions may unacceptably increase execution time. In this paper we focus on a number of experiments with schemes for error detection, having a 3D Path Planning application for an avionics system as case study. We analyze how these error detection schemes can be implemented to meeting system's time budget. The experiments allowed us to acquire the requirements for automating the application of the error detection schemes in the context of a hardware/software design-flow, and to determine how those schemes can be addressed using a novel approach where safety requirements are described using an aspect- and strategy-oriented programming language, named LARA. For our experiments and validation, we consider an FPGA-based embedded system consisting of a general purpose processor (GPP) coupled to custom computing units which are primarily used for hardware acceleration and for implementing fault detection schemes. © 2012 IEEE.