Cookies Policy
The website need some cookies and similar means to function. If you permit us, we will use those means to collect data on your visits for aggregated statistics to improve our service. Find out More
Accept Reject
  • Menu
Publications

Publications by José Boaventura

2002

Evaluation of Plant Growth Models for a Soil Greenhouse Tomato Crop

Authors
V. Fernandes and J. Boaventura Cunha,;

Publication
World Congress of Computers in Agriculture and Natural Resources, Proceedings of the 2002 Conference

Abstract

2011

A Support Tool for Teaching Grafcet: Engineering Students’ Perceptions

Authors
Lea~o, CP; Soares, FO; Machado, J; de Moura Oliveira, PB; Boaventura Cunha, J;

Publication
Volume 5: Engineering Education and Professional Development

Abstract

2008

Fractional electrical impedances in botanical elements

Authors
Jesus, IS; Machado, JAT; Cunha, JB;

Publication
JOURNAL OF VIBRATION AND CONTROL

Abstract
Fractional calculus (FC) is no longer considered solely from a mathematical viewpoint, and is now applied in many emerging scientific areas, such as electricity, magnetism, mechanics, fluid dynamics, and medicine. In the field of dynamical systems, significant work has been carried out proving the importance of fractional order mathematical models. This article studies the electrical impedance of vegetables and fruits from a FC perspective. From this line of thought, several experiments are developed for measuring the impedance of botanical elements. The results are analyzed using Bode and polar diagrams, which lead to electrical circuit models revealing fractional-order behaviour.

2005

Fractional dynamic fitness functions for GA-based circuit design

Authors
Reis, C; Tenreiro Machado, JAT; Boaventura Cunha, JB;

Publication
GECCO 2005: Genetic and Evolutionary Computation Conference, Vols 1 and 2

Abstract
This paper proposes and analyses the performance of a Genetic Algorithm (GA) using two new concepts, namely a static fitness function including a discontinuity measure and a fractional-order dynamic fitness function. The GA is adopted for the synthesis of combinational logic circuits. In both cases, experiments reveal superior results in terms of speed and convergence to achieve a solution.

1997

A computer-based fuzzy temperature controller for environmental chambers

Authors
Salgado, P; Cunha, JB; Couto, C;

Publication
ISIE '97 - PROCEEDINGS OF THE IEEE INTERNATIONAL SYMPOSIUM ON INDUSTRIAL ELECTRONICS, VOLS 1-3

Abstract
This paper describes a computer-based temperature control system for an environmental chamber. The identification of the thermal process was made from the analysis of the collected output data in response to random generated input signals. Using this model it was established the optimal linear and non linear control strategies in order to achieve the desired set-point and to minimize the number of actuations. The actuation over the heating and cooling systems were performed with conventional PID and fuzzy controllers and their responses were compared. This work enhances fuzzy controllers application with self-learning capability to achieve the prescribed control objectives in a near-optimal manner. By applying back-propagation through time it was possible to force the plant block to generate the desired trajectory.

2007

Evolutionary computation in the design of logic circuits

Authors
Reis, C; Machado, JAT; Cunha, JB; Pires, EJS;

Publication
2007 IEEE INTERNATIONAL CONFERENCE ON SYSTEMS, MAN AND CYBERNETICS, VOLS 1-8

Abstract
This paper presents two evolutionary schemes and a swarm intelligence algorithm for the design of combinational logic circuits. A Genetic and a Memetic schemes as the evolutionary algorithms. The Particle Swarm Optimization as the swarm algorithm. The fitness function used in these three algorithms is sequential, that is, divided in two parts. The first part of the fitness function f(1) evaluates the circuit functionality, while the second part f(2) deals with the circuit complexity. The experiments consist in applying the algorithms in the design of two arithmetic circuits: the one-bit full adder and the one-bit full subtractor. We also present a scalability analysis using the parity checker family of circuits.

  • 16
  • 24