Abstract
Higher-order statistics (HOS) are a powerful analysis tool in digital signal processing. The most difficult task to use it effectively is the estimation of higher-order moments of sampled data, taken from real systems. For applications that require real-time processing, the performance achieved by common microprocessors or digital signal processors is not good enough to carry out the large number of calculations needed for their estimation. This paper presents ProHos-1, an experimental vector processor for the estimation of the higher-order moments up to the fourth-order. The processor's architecture exploits the structure of the algorithm, to process in parallel four vectors of the input data in a pipe-lined fashion, executing the equivalent to 11 operations in each clock cycle. The design of dedicated control circuits led to high clock rate and small hardware complexity, thus suitable for implementation as an ASIC (Application Specific integrated Circuit).

Abstract
This paper describes the design of a processor specific for testing cores embedded in system-on-chip. This processor which can be implemented within a system's reconfigurable area, shall be responsible for scheduling and control test operations and perform preliminary data processing, as well as to provide the interface with an external tester Building these test operations on-chip allows for simplifying external tester interface and to reduce testing time. The testing procedure and the infrastructure required to test an AID converter is described as an example.

Abstract

Abstract