Abstract
The sheer size of data sets from application domains such as biomedical and social networks will lead to the need to develop algorithms that have strict time bounds and can tolerate temporary unavailability of data if they are to produce acceptable results in feasible time. In this paper we describe a simple, yet powerful, object-based concurrent programming model that features atomicity, timed execution and tolerance to data unavailability. We describe the underlying concepts and illustrate their use in a sample computation on large graphs. This experience shows that it is possible to augment existing concurrent programming models to support developers in developing and reasoning about incomplete computations, we believe, will become, an increasingly important class of algorithms. © 2015 IEEE.

Abstract
Cache parameters such as size and associativity are fixed at manufacturing time which are often not tuned for the speciffc characteristics of each application code. The net re-sult is excessive energy consumption and lower performance. This paper explores the benefits of the use of a reconfig-urable data cache in terms of capacity and associativity in a LEON-3 embedded system. We present real energy and execution time results for a set of graph-based and numer-ical algorithms. For a combined application of these algo-rithms, the results reveal an aggregate energy savings of 7% and a execution time penalty of just 1% over the best fixed-Associativity cache architecture with the same capacity. We further explore the performance of a dynamic cache way shutdown adaptive algorithm and evaluate its performance and energy benefits in the context of the SLAM-EKF posi-tion estimation robotics algorithm. © 2015 ACM.

Abstract
There is an increasing concern about transient errors in deep submicron processor architectures. Softwareonly error detection approaches that exploit program invariants for silent error detection incur large execution overheads and are unreliable as state can be corrupted after invariant checkpoints. In this article, we explore the use of configurable hardware structures for the continuous evaluation of high-level program invariants at the assembly level. We evaluate the resource requirements and performance of the proposed predicate-evaluation hardware structures when integrated with a 32-bit MIPS soft core on a contemporary reconfigurable hardware device. The results, for a small set of kernel codes, reveal that these hardware structures require a very small number of hardware resources with negligible impact on the processor core that they are integrated in. Moreover, the amount of resources is fairly insensitive to the complexity of the invariants, thus making the proposed structures an attractive alternative to software-only predicate checking. Copyright © 2015 ACM.

Abstract

Abstract
This study describes and evaluates an automated technique that exploits the potential of heterogeneous multi-core processor (HMP) systems when customised with respect to the number of cores and L1 cache memory sizes using a field programmable gate array fitted with LEON3 cores at its base. The authors evaluated the real energy consumption of the HMP system tuned for a set of 50 application codes using a data-mining tool for finding code similarities and selecting HMP configurations. The selected HMP system configuration requires a small cache configuration and consumes less energy when compared to a homogeneous system with the same number of cores and only with a very modest increase in execution time. © The Institution of Engineering and Technology 2015.