Abstract
This work presents the design and analysis of a biological signal processing accelerator, including an interface controller and memory subsystem for a low-power CGRA. The controller design supports several operation modes, which can perform several applications when paired with the CGRA reconfiguration capabilities. Physical synthesis shows that the controller introduces only a 6 percent area and power overhead compared to the CGRA core, while allowing independent processing of inner loops at high frequencies and the exploitation of pipelining and parallelism. In-depth power analysis based on layout information was performed, including an evaluation of the use of power gating techniques. A practical case study (ECG signal processing) was also evaluated. © 2018 IEEE.