Abstract

Abstract
This paper presents experiments carried out with a prototype test chip provided by the IEEE P1149.4 Mixed-Signal Testing Working Group, which explore the architecture of the proposed analogue boundary module to implement simultaneous observation of power supply current and output voltage, towards mixed current/voltage testing of analogue and mixed-signal circuits.

Abstract
Higher-order statistics (HOS) are a powerful analysis tool in digital signal processing. The most difficult task to use it effectively is the estimation of higher-order moments of sampled data, taken from real systems. For applications that require real-time processing, the performance achieved by common microprocessors or digital signal processors is not good enough to carry out the large number of calculations needed for their estimation. This paper presents ProHos-1, an experimental vector processor for the estimation of the higher-order moments up to the fourth-order. The processor's architecture exploits the structure of the algorithm, to process in parallel four vectors of the input data in a pipe-lined fashion, executing the equivalent to 11 operations in each clock cycle. The design of dedicated control circuits led to high clock rate and small hardware complexity, thus suitable for implementation as an ASIC (Application Specific integrated Circuit).

Abstract

Abstract

Abstract
Reducing the area overhead required by BIST structures can be achieved by reconfiguring existing hardware to perform test related control and processing functions. This work shows how the resources required for these operations can be implemented in-circuit, taking advantage of programmable logic available in the system. Structural and functional tests are performed using correlation to obtain iDD and uOUT cross-correlation signatures, and to measure gain, phase, and total harmonic distortion. © 2000 IEEE.