Abstract
We present the disparity map computation core of a hardware system for isolating foreground objects in stereoscopic video streams. The operation is based on the computation of dense disparity maps using block-matching algorithms and two well-known metrics: sum of absolute differences and Census transform. Two sets of disparity maps are computed by taking each of the images as reference so that a consistency check can be performed to identify occluded pixels and eliminate spurious foreground pixels. Taking advantage of parallelism, the proposed architecture is highly scalable and provides numerous degrees of adjustment to different application needs, performance levels and resource usage. A version of the system for 640 x 480 images and a maximum disparity of 135 pixels was implemented in a system based on a Xilinx Virtex II-Pro FPGA and two cameras with a frame rate of 25 fps (less than the maximum supported frame rate of 40 fps on this platform). Implementation of the same system on a Virtex-5 FPGA is estimated to achieve 80 fps, while a version with increased parallelism is estimated to run at 140 fps (which corresponds to the calculation of more than 5.9 x 10(9) disparity-pixels per second).

Abstract
The paper presents the approach followed at the Faculty of Engineering of the University of Porto, to introduce design automation tools and structured design techniques in the first course on digital system design of our Integrated Master in Electrical and Computer Engineering. Digital Systems Laboratory is an introductory course on digital design, with the classical task of teaching Boolean algebra and combinational and sequential circuit design, using gates, flip-flops and medium complexity components/function blocks like counters and shift-registers. The need to cope with new curriculum requirements and modern digital design demands, motivated an extensive reformulation of the course contents and organization, leading to the introduction of the use of hardware description languages and synthesis tools, in order to implement small systems, of increasingly complex nature, on an FPGA platform. At the same time its coverage was extended to include low-level processor architecture issues, and to teach assembly programming for the MIPS processor. The paper describes how this reformulation was carried out. It presents the course contents and timeline, and discusses the main choices that were made. The paper also describes the laboratory experiments that were developed and discusses some of the challenges and results obtained so far. © 2014 IEEE.

Abstract
This work presents RVC (Reconfigurable Vector Coprocessor), a FPGA based custom computing machine for vector processing applications. This system was built to serve as an implementation platform for a custom vector processor designed for a digital signal processing application. Although its architecture has been in part dictated by the immediate needs of that dedicated processor, it also serves for other custom machines exhibiting similar requirements of vector processing. © 1998 IEEE.

Abstract
An account is given on the joint time-frequency analysis (JTFA) and the short time-frequency transform algorithm in particular as an alternative technique for dynamic testing of analog to digital converters (ADCs). It is shown that this technique can lead to a significant improvement in ADC testing mainly due the possibility of using non-stationary signals allowing a more rapid test capable of analyzing even localized features.

Abstract

Abstract
ReDiFlex is a system that supports the development of applications that use dynamically and partially-reconfigurable hardware. The hardware functionality is specified by the flow of data between mutable operators. The system automatically creates the physical implementation after partitioning the model to fit the hardware constraints; during application execution new computation-dependent partial configurations can be created. ReDiFlex provides run-time support for reconfiguration and data transfer scheduling.