Abstract
The nesting (or placement) problem is an NP-hard combinatorial problem with important industrial applications, e.g. in apparel or footwear industry. This paper describes a hardware infrastructure to accelerate the processing of the underlying geometric information. The system consists of an FPGA-based reconfigurable platform enhanced by an ASIC for the processing of irregular polygons. The paper discusses the need for such a platform, establishes the main design guidelines and describes the architecture and modes of operation of both the reconfigurable infrastructure and the dedicated IC.

Abstract
The nesting problem consists of defining the cutting plan of a piece of raw material in smaller irregular shapes, and has applications in the apparel and footwear industries. Due to its NP-hard nature, the optimal solution can only be guaranteed by exhaustively trying all possible solutions and choosing the best one. Because this is impractical in real-life industrial problems, automatic approaches are based on optimization meta-heuristics that search for sub-optimal but good enough solutions. These optimization techniques rely on the construction and evaluation of several solutions, thus requiring heavy geometric manipulation of the irregular polygons that constitute the problem data. Efficient processing of this geometric information is thus necessary to make effective fully automatic approaches to nesting problems in industrial environments. This paper describes Fafner, an FPGA-based custom computing machine that is used to accelerate the geometric operations, that are in the core of heuristic solutions to the nesting problem. The system is used as an auxiliary processor attached to a low cost personal computer, and combines a custom programmable processor with an array of custom circuits for the processing of irregular polygons.

Abstract

Abstract
ReDiFlex is a system that supports the development of applications that use dynamically and partially-reconfigurable hardware. The hardware functionality is specified by the flow of data between mutable operators. The system automatically creates the physical implementation after partitioning the model to fit the hardware constraints; during application execution new computation-dependent partial configurations can be created. ReDiFlex provides run-time support for reconfiguration and data transfer scheduling.

Abstract
BST is a well established standard and testability framework for digital ICs and boards. The paper presents a test support IC controlled by an IEEE1149.1 interface, capable of providing access to analog nodes in mixed-signal boards. The proposed architecture (ABSINT - Analog to Boundary Scan Interface) is described and relevant implementation issues are discussed. A demonstrator IC implementing the ABSINT architecture is presented, and it is shown how it can be used to provide analog test channels under control of IEEE1149.1.

Abstract
This paper proposes a method to avoid using a CORDIC or external memory to process the steering vectors to calculate the pseudospectrum of correlation-based beamforming algorithms. We show that if we decompose the steering vector equation, the size of the matrix to be saved in memory becomes independent of the antenna array size. Besides, the amount of data needed is small enough to be saved in the internal block RAMs of the FPGA SoC. Besides, this method greatly reduces the number of memory accesses, by offloading some processing to hardware, while keeping the frequency at 300MHz with a precision of 0.25°. Finally, we show that this approach is scalable since the complexity grows logarithmically for bigger arrays, and the symmetry in the matrices obtained allows even more compact data. © 2024 IEEE.