Abstract
Computer architecture is an important subject for informatics and electrical engineering courses. However, students display some difficulties in this subject, mainly due to the lack of educational tools that are intuitive, versatile and graphical. Existing tools are not adequate enough or are very specific. In this paper, an educational MIPS simulator, DrMIPS, is described. This tool simulates the execution of an assembly program on the CPU and displays the datapath graphically. Registers, data memory and assembled code are also displayed and a "performance mode" is also provided. Both unicycle and pipeline implementations are supported and the CPUs and their instruction sets are configurable. The tool is currently available for PCs and Android tablets, and is fairly intuitive and versatile on both platforms.

Abstract
Cognitive Radios (CR) are viewed as a solution for spectrum utilization and management in next generation wireless networks. In order to adapt themselves to the actual communications environment, CR devices require highly flexible baseband processing engines. One of the most relevant operations involved in radio baseband processing is the FFT. This work presents a reconfigurable FFT processor supporting FFT sizes and throughputs required by the most used wireless communication standards. By employing Dynamic Partial Reconfiguration (DPR), the implemented design can adapt the FFT size at run-time and specialize its operation to the immediate communication demands. This translates to hardware savings, enhanced resource usage efficiency and possible power savings. The results obtained for reconfiguration times suggest that DPR techniques are a viable option for designing flexible and adaptable baseband processing components for CR devices. © Springer International Publishing Switzerland 2016.

Abstract
The proliferation of new wireless communication technologies and services led to a boost in the number of different available communication standards and spectrum usage. As the electromagnetic spectrum is a finite resource, concerns about its efficient management became an important aspect. Given this scenario, Cognitive Radio emerged as a solution for future wireless communication devices, by supporting multiple standards and improving spectrum utilization through opportunistic wireless access. The purpose of this research is to study and design a reconfigurable FPGA-based NC-OFDM baseband processor meeting the requirements of next generation Cognitive Radio devices in terms of multi-carrier, multi-standard communications and spectral agility in changing environments. The processor will be the core of a flexible NC-OFDM transceiver for future 5G communications with support for spectrum aggregation and run-time selection of modulation schemes and active sub-carriers. The goal is to achieve higher levels of system adaptability, upgradeability and efficiency, by employing dynamic partial reconfiguration of FPGAs.

Abstract
This paper describes and evaluates a fully digital circuit for one-way master-to-slave highly precise time synchronization in a low-power, wearable system equipped with a set of sensor nodes connected in a mesh network. Sensors are connected to each other with conductive yarns that are used as one-wire bidirectional communication links. The circuit is designed to perform synchronization in the Medium Access Control (MAC) layer. In each sensor node, the synchronization circuit provides a synchronized, programmable clock signal and a real-time counter for time stamping. Experimental results obtained with an implementation in 0.35 mu m CMOS technology for a network of electromyography sensors show that the circuit keeps the one-hop average clock skew below 4.6 ns, a value small enough to satisfy many wearable application requirements.

Abstract
The acceleration of applications, running on a general purpose processor (GPP), by mapping parts of their execution to reconfigurable hardware is an approach which does not involve program's source code and still ensures program portability over different target reconfigurable fabrics. However, the problem is very challenging, as suitable sequences of GPP instructions need to be translated/mapped to hardware, possibly at runtime. Thus, all mapping steps, from compiler analysis and optimizations to hardware generation, need to be both efficient and fast. This paper introduces some of the most representative approaches for binary acceleration using reconfigurable hardware, and presents our binary acceleration approach and the latest results. Our approach extends a GPP with a Reconfigurable Processing Unit (RPU), both sharing the data memory. Repeating sequences of GPP instructions are migrated to an RPU composed of functional units and interconnect resources, and able to exploit instruction-level parallelism, e.g., via loop pipelining. Although we envision a fully dynamic system, currently the RPU resources are selected and organized offline using execution trace information. We present implementation prototypes of the system on a Spartan-6 FPGA with a MicroBlaze as GPP and the very encouraging results achieved with a number of benchmarks.

Abstract
The ability to map instructions running in a microprocessor to a reconfigurable processing unit (RPU), acting as a coprocessor, enables the runtime acceleration of applications and ensures code and possibly performance portability. In this work, we focus on the mapping of loop-based instruction traces (called Megablocks) to RPUs. The proposed approach considers offline partitioning and mapping stages without ignoring their future runtime applicability. We present a toolchain that automatically extracts specific trace-based loops, called Megablocks, from MicroBlaze instruction traces and generates an RPU for executing those loops. Our hardware infrastructure is able to move loop execution from the microprocessor to the RPU transparently, at runtime, and without changing the executable binaries. The toolchain and the system are fully operational. Three FPGA implementations of the system, differing in the hardware interfaces used, were tested and evaluated with a set of 15 application kernels. Speedups ranging from 1.26 × to 3.69 × were achieved for the best alternative using a MicroBlaze processor with local memory. © 2013 João Bispo et al.