Abstract
This paper describes and evaluates a fully digital circuit for one-way master-to-slave, highly precise time synchronization in a low-power wearable system equipped with a set of sensor nodes. These sensors are connected to each other in a mesh topology, with conductive yarns used as one-wire bidirectional communication links. The circuit is designed to perform synchronization in the MAC layer, so that the deterministic part of the clock skew between nodes is kept constant and compensated with a single message exchange. In each sensor node, the synchronization circuit provides a programmable clock signal and a real-time counter for time stamping. Experimental results from a fabricated ASIC (in a CMOS 0.35 mu m technology) show that the circuit keeps the one-hop average clock skew below 4.6 ns and that the skew grows linearly as the hop distance to the reference node increases. The sub-microsecond average clock skew achieved by the proposed solution satisfies the requirements of many wearable sensor network applications.

Abstract
The genetic algorithm is a general purpose optimization metaheuristic for solving complex optimization problems. Because the algorithm usually requires a large number of iterations to evolve a population of solutions to good final solutions, it normally exhibits long execution times, especially if running on low-performance conventional processors. In this work, we present a scalable computing array to parallelize and accelerate the execution of cellular GAs (cGAs). This is a variant of genetic algorithms which can conveniently exploit the coarse-grain parallelism afforded by custom parallel processing. The proposed architecture targets Xilinx FPGAs and was implemented as an auxiliary processor of an embedded soft-core CPU (MicroBlaze). To facilitate the customization for different optimization problems, a high-level synthesis design flow is proposed where the problem-dependent operations are specified in C++ and synthesised to custom hardware, thus demanding of the programmer only minimal knowledge of low-level digital design for FPGAs. To demonstrate the efficiency of the array processor architecture and the effectiveness of the design methodology, the development of a hardware solver for the minimum energy broadcast problem in wireless ad hoc networks is employed as a use case. Implementation results for a Virtex-6 FPGA show significant speedups, especially when comparing to embedded processors used in current FPGA devices.

Abstract
This paper describes the design and implementation of a coarse-grained reconfigurable array (CGRA) for low-power biological signal processing. It uses an use-case-driven approach which explores the application domain and gathers common requirements. The selected CGRA core architecture is implemented using a standard-cell flow (in a generic 90nm CMOS process), so that the CGRA can be totally or partially turned off by power gating. The selected CGRA design is evaluated for two use-cases using layout information and accurate node activity information. The resulting accelerator is capable of performing various signal processing tasks very efficiently, achieving an average power consumption of 19.9 pJ/cycle (or 1.99mW at 100 MHz). Static power consumption for less intensive tasks can be reduced by using only some sections of the CGRA while powering-off others.

Abstract
This paper proposes a new open-loop and low complexity (small size) fast-lock synchronization circuit for clock and data recovery in wearable systems. The system includes sensors embedded in textile and connected by conductive yarns. Synchronization is based on the open-loop selection of the correct phase of the receiver clock synchronously with the incoming signal. The clock generator of the receiver is an autonomous oscillator set to operate at the same nominal frequency. The circuit lock time is at most one clock cycle, faster than all methods based on phase-locked loops or delay-locked loops. The circuit can be used for baseband communication independently of the signal coding method used in the physical layer, making it suitable for many applications. The fully digital circuit (including non-return-to-zero inverted decoder) occupies 0.0022 in a 0.35 complementary metal-oxide semiconductor (CMOS) process, a smaller implementation than many existing circuits, and supports a maximum system clock frequency of 70 for a 35-data rate. Experimental results demonstrate that the proposed circuit robustly generates a synchronous clock for data recovery. The circuit is suitable for systems that tolerate some jitter but requires fast lock time, small size, and low energy consumption. Copyright (c) 2015 John Wiley & Sons, Ltd.

Abstract

Abstract
This paper presents a network router and transceiver for wearable, low-power, high-speed Body Area Networks (BAN) applications running in a mesh network of sensors embedded in textiles and connected to each other with conductive yarns functioning as bidirectional transmission channels. The routing of data packets from sensor nodes to a sink node is based on hybrid circuit and packet switching. In comparison with pure packet switching, hybrid routing decreases end-to-end delay, power consumption and buffer size. The proposed design uses independent sender, receiver and circuit switching modules, thereby allowing the nodes to simultaneously send and receive data. The simulation results show that circuit and hybrid switching modes significantly increase the performance of the system. In addition, implementing the complete packet process on FPGA, instead of using an external microcontroller as in previous work, enables a much faster routing process. The results are based on a Verilog description of the system, which has been synthesized for a low-power IGLOO FPGA with Libero Project Manager and simulated with ModelSim. The implementation operates successfully at a data rate of 20 Mbps.