Abstract
This paper addresses a modeling and simulation methodology for analog circuit design with amorphous-GIZO thin-film transistors (TFTs). To reach an effective circuit design flow, with commercially available tools, a TFT model has been first developed with an artificial neural network (ANN). Multilayer perceptron with backpropagation algorithm has been adopted to model the static behavior of the TFT devices, for different aspect ratios. The model was then implemented in Verilog-A, to allow a quick instantiation in circuit. Simulations using Cadence Spectre are performed to validate the model. On a second phase, simulation results of basic analog circuits, with this ANN model, are verified against the actual functional results, namely an adder, subtractor, and current mirror circuit. Results demonstrate not only the ANN model accuracy and compatibility with dc and transient analysis, but also show the a-GIZO TFT capability to perform analog operations. © 2012 IEEE.

Abstract
This paper presents an initiative to involve ECE undergraduate students in the design and deployment of a network infrastructure for an academic laboratory. The project aims at attaining a reliable and secure network for an IC CAD environment. The students focused on employing secure authentication, accounting and storage with single sign-on, based on enterprise-grade, open-source protocols. This initiative proved to be highly motivating and allowed the students to develop knowledge and hands-on experience on the area of network security. The resulting network design and core infrastructure is herein described as well as its deployment in a real microelectronics design environment. © 2011 IEEE.

Abstract
A new CMOS VLSI implementation of an asymmetric programmable sigmoid neural activation function, as well as of its derivative, is presented. It consists of two coupled PMOS and NMOS differential pairs with different programmable bias currents that set the upper and lower limits of the sigmoid. The circuit works in the weak inversion region, for low power consumption and exponential envelope, or in strong inversion to achieve higher speeds. The results obtained from the theoretical transfer function, and from the simulations of the circuit implemented in AMI's 0.35 mu m technology, show a very good match.

Abstract
This paper presents the results of a CMOS-VLSI implementation of a realistic computational model proposed by Walter Freeman for the olfactory system. This model, in later years, has been studied for engineering applications such as auto-association and classification. The analogue nature of the model motivates analogue VLSI implementations. However, the dimension and complexity of such system poses many obstacles to an analogue electronic implementation; one such is the massive interconnectivity which size increases with the square of the number of inputs (channels). We suggest a multiplexing procedure that puts the burden of interconnectivity over a digital system that is simpler to design and makes the analogue system more treatable. The procedure naturally samples the signals. To avoid smoothing filters, a discrete-time solution was also employed. Although with such approach the time resolution is reduced, the advantages overcome the detriments. Previous work has shown that the model can be efficiently discretized using DSP techniques, resulting on a system that is able to predict, on sample-by-sample basis, the behaviour of the VLSI circuit, allowing for a simple and flexible way to adjust the circuit parameters. We present the measured circuit results that are further confronted with the digital implementation.

Abstract

Abstract
A system for the detection of spikes and sharp waves (SSWs) in EEGs of epileptic patients is described. The system uses a pattern recognition technique and it is implemented in a hybrid microcomputer. It performs the on-line simultaneous analysis of 4 EEG channels and thus it is appropriate for long-term EEG recording. The performance of the system was considered satisfactory when compared with that of a panel of electroencephalographers. © 1983.