Abstract
The use of power Darlington transistors for an inverter of a 40-kVA uninterruptible power supply (UPS) system is discussed, and the storage time, dead time, and switching aid network contributions to the total harmonic content of the output voltage are examined. A review of common switching aid circuits, for nominal and short-circuit conditions, is presented, and their limitations are discussed. A solution, conceived specifically for power Darlington transistors, is presented. The solution that fits the most relevant characteristics of this technology is analyzed regarding commutation under nominal conditions, commutation under short-circuit conditions, and contribution to harmonic distortion in the output voltage. Conclusions are drawn about the optimal switching frequency for this type of application. The discussion and conclusions are supported by experimental and simulation results.

Abstract
Different built-in self testing schemes for RF circuits have been developed resorting to peak voltage detectors. These are simple to implement but provide a conditional RF power measurement accuracy as impedance is assumed to be known. A true power detector is presented which allows obtaining more accurate measurements, namely as far as output load variations are concerned. The theoretical fundaments underlining the power detector operating principle are presented and simulation and experimental results obtained with a prototype chip are described which confirm the benefits of measuring true power, comparing to output peak voltage, when observing output load matching deviations and complex waveforms.

Abstract
Supply current test is well established for digital CMOS circuits and the advantages of improved observability and reliability indication have prompted its use for analogue and mixed signal circuits. A short review of the literature on this subject is given. Fault simulation is used for the investigation of dynamic supply current test of a PLL, confirming existing results from smaller circuits that a combination of supply current and output voltage monitoring leads to higher fault coverage. In the paper, fault coverage is further improved, using crosscorrelation of the supply current and output signals, and the potential for BIST implementation of this technique is demonstrated using low resolution polarised crosscorrelation. Fault simulation is also performed on an analogue multiplier to investigate the effect of process parameter deviations on the supply current. The fault coverage is found to be improved by removing the DC component of the signal. Encouraging results are obtained from the application of supply current test techniques to a commercial mixed signal ASIC currently beyond the capabilities of analogue fault simulation, indicating that efforts at improving fault simulation in this area are worthwhile. The requirements for fault modelling and simulation to support supply current test are discussed and some initial results of accelerating this process using macromodelling are presented.

Abstract
Endoleaks are one of the major concerns in the long-term follow-up of endovascular aneurysm repair treatment (EVAR). Therefore, periodic monitoring is required to detect eventual damages in an implanted stent-graft. A monitoring system for post EVAR procedure based on inductive-coupling which avoids the need to resorting to more complex biomedical imaging systems is presented here. Endoleaks are detected with capacitive pressure sensors placed in the stent-graft and monitored externally after the measure of the oscillation frequency provided by the LC circuit created by sensors and inductive coupling.

Abstract
The cross-correlation between i(DD) and v(out) signals is addressed as a means for improving the testing of analogue circuits. Besides the higher testing confidence provided by mixed i(DD)/v(out) monitoring, a single unified test operation is performed instead of two separate operations.

Abstract
Test stimuli generation and power consumption are two Issues that jeopardize the design of built-in self test schemes. The LNA testing approach presented herein relies on converting the amplifier Into an oscillator and on using a low-power correlator to obtain a signature from the cross-correlation between the dynan-dc power supply current and the LNA's output voltage. In test mode a high fault coverage is obtained together with a low power consumption, while avoiding an extra stimulus generator. No significant performance degradation results from the added test circuitry. Concerning the Interface with the external tester, a digital signal is required to switch between normal and test modes, as well as a low frequency line to capture the correlator DC output voltage.