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This chapter describes the CoSy1-based [1, 2] compilers developed in the context of the REFLECT project to support its aspect-oriented design-flow. In particular, these CoSy-based compilers are guided by LARA strategies and are responsible for generating code targeting traditional processors, as well as generating behavioral-RTL VHDL code [3] targeting hardware accelerators. Throughout this chapter, these compilers are referred collectively as reflectc, except when a specific compilation flow (with its specific name) is used. We also describe the compiler development extensions to support the REFLECT approach [4] and the weaving process controlled by LARA strategies [5-7] as described in Chap. 3. © Springer Science+Business Media New York 2013. All rights are reserved.

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This chapter presents the most relevant related work with respect to the compilation and synthesis approach developed in the context of the REFLECT project. We survey current techniques and methodologies for the mapping of computations described in high-level programming languages to reconfigurable architectures. We give particular emphasis to compilation systems that map imperative (C-like) languages to target FPGA-based systems. We also describe previous work on compiler optimizations, automated high-level synthesis, and strategies for back-end synthesis, mapping as well as placement and routing. Finally, we include an overview of EU-funded projects relevant to REFLECT. © Springer Science+Business Media New York 2013. All rights are reserved.

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The compilation of high-level languages, such as software programming languages, to FPGAs is of paramount importance for the mainstream adoption of FPGAs. An efficient compilation process will improve designer productivity and will make the use of FPGA technology viable for software programmers. When targeting the hardware resources provided by FPGAs, a compilation process usually requires a stage known as High-Level Synthesis (HLS) which is responsible for generating application specific hardware architectures from the input source code or from an intermediate representation of the input application. This chapter briefly describes HLS and its main processing stages. The chapter provides the indispensable knowledge for readers who want to follow the remaining chapters of this book. © Springer International Publishing Switzerland 2016.