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Publications

Publications by João Paiva Cardoso

2017

Introduction to the special issue on architecture of computing systems

Authors
Hannig, F; Cardoso, JMP; Fey, D;

Publication
JOURNAL OF SYSTEMS ARCHITECTURE

Abstract

2015

ANTAREX - AutoTuning and Adaptivity appRoach for Energy efficient eXascale HPC systems

Authors
Silvano, C; Agosta, G; Bartolini, A; Beccari, A; Benini, L; Cardoso, JMP; Cavazzoni, C; Cmar, R; Martinovic, J; Palermo, G; Palkovic, M; Rohou, E; Sanna, N; Slaninova, K;

Publication
2015 IEEE 18TH INTERNATIONAL CONFERENCE ON COMPUTATIONAL SCIENCE AND ENGINEERING (CSE)

Abstract
The main goal of the ANTAREX project is to express by a Domain Specific Language (DSL) the application self-adaptivity and to runtime manage and autotune applications for green and heterogeneous High Performance Computing (HPC) systems up to the Exascale level. Key innovations of the project include the introduction of a separation of concerns between self-adaptivity strategies and application functionalities. The DSL approach will allow the definition of energy-efficiency, performance, and adaptivity strategies as well as their enforcement at runtime through application autotuning and resource and power management.

2017

Proceedings of the 1st Workshop on AutotuniNg and aDaptivity AppRoaches for Energy efficient HPC Systems, ANDARE@PACT 2017, Portland, OR, USA, September 9, 2017

Authors
Bartolini, A; Cardoso, JMP; Silvano, C;

Publication
ANDARE@PACT

Abstract

2014

High-Level Synthesis from C vs. a DSL-based Approach

Authors
de Oliveira, CB; Marques, E; Cardoso, JMP;

Publication
PROCEEDINGS OF 2014 IEEE INTERNATIONAL PARALLEL & DISTRIBUTED PROCESSING SYMPOSIUM WORKSHOPS (IPDPSW)

Abstract
Field-Programmable Gate Arrays (FPGAs) are able to provide hardware accelerators still maintaining the required programmability. However, the advantages of using FPGAs still depend on the expertise of developers and their knowledge of Hardware Description Languages (HDLs). Although High-level Synthesis (HLS) tools have been developed in order to minimize this problem, they commonly present solutions considered many times inefficient when compared to the ones achieved by a specialized hardware designer. Domain-specific languages (DSLs) can provide alternative solutions to program FPGAs. They can provide higher abstraction levels than HDLs and they may allow the programmer to tune implementations whenever HLS tools are unable to generate efficient designs. In this paper we compare a DSL, named LALP (Language for Aggressive Loop Pipelining), with two typical HLS approaches and show the experimental results achieved in each case. The results show that the use of LALP provides superior performance than the achieved by the HLS tools in most cases.

2014

Message from general and program chairs

Authors
Silvano, C; Cardoso, JMP; Huebner, M;

Publication
ACM International Conference Proceeding Series

Abstract

2017

Message from general and program co-chairs

Authors
Cardoso, JMP; Huebner, M; Agosta, G; Silvano, C;

Publication
ACM International Conference Proceeding Series

Abstract

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