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Publications

Publications by Luis Miguel Pinho

2013

Revisiting transactions in Ada

Authors
Barros, A; Pinho, LM;

Publication
ACM SIGAda Ada Letters

Abstract
Classical lock-based concurrency control does not scale with current and foreseen multi-core architectures, opening space for alternative concurrency control mechanisms. The concept of transactions executing concurrently in isolation with an underlying mechanism maintaining a consistent system state was already explored in fault-tolerant and distributed systems, and is currently being explored by transactional memory, this time being used to manage concurrent memory access. In this paper we discuss the use of Software Transactional Memory (STM), and how Ada can provide support for it. Furthermore, we draft a general programming interface to transactional memory, supporting future implementations of STM oriented to real-time systems.

2014

Non-preemptive Scheduling of Real-Time Software Transactional Memory

Authors
Barros, A; Pinho, LM;

Publication
Architecture of Computing Systems - ARCS 2014 - 27th International Conference, Lübeck, Germany, February 25-28, 2014. Proceedings

Abstract
Recent embedded processor architectures containing multiple heterogeneous cores and non-coherent caches, bring renewed attention to the use of Software Transactional Memory (STM) as a building block for developing parallel applications. STM promises to ease concurrent and parallel software development, but relies on the possibility of abort conflicting transactions to maintain data consistency, which affects the execution time of tasks carrying transactions. Thus, execution time overheads resulting from aborts must be limited, otherwise the timing behaviour of the task set will not be predictable. In this paper we formalise a FIFO-based algorithm to order the sequence of commits of concurrent transactions. Furthermore, we propose and evaluate two non-preemptive scheduling strategies, in order to avoid transaction starvation. © 2014 Springer International Publishing Switzerland.

2017

The EnerGAware Middleware Platform

Authors
Barbosa, P; Barros, A; Pinho, LM;

Publication
IECON 2017 - 43RD ANNUAL CONFERENCE OF THE IEEE INDUSTRIAL ELECTRONICS SOCIETY

Abstract
More and more cyber-physical systems and the internet of things push for a multitude of devices and systems, which need to work together to provide the services as required by the users. Nevertheless, the speed of development and the heterogeneity of devices introduces considerable challenges in the development of such systems. This paper describes a solution being implemented in the setting of a serious game scenario, connected to real homes energy consumption. The solution provides a publish-subscribe middleware which is able to seamlessly connect all the components of the system.

2016

Response time analysis of hard real-time tasks sharing software transactional memory data under fully partitioned scheduling

Authors
Barros, A; Yomsi, PM; Pinho, LM;

Publication
2016 11TH IEEE INTERNATIONAL SYMPOSIUM ON INDUSTRIAL EMBEDDED SYSTEMS (SIES)

Abstract
Software transactional memory (STM) is a synchronisation paradigm which improves the parallelism and composability of modern applications executing on a multi-core architecture. However, to abort and retry a transaction multiple times may have a negative impact on the temporal characteristics of a real-time task set. This paper addresses this issue: It provides a framework in which an upper-bound on the worst-case response time of each task is derived, assuming that tasks are scheduled by following either the Non-Preemptive During Attempt (NPDA), Non-Preemptive Until Commit (NPUC) or Stack Resource Policy for Transactional Memory (SRPTM) policy.

2015

Non-preemptive and SRP-based fully-preemptive scheduling of real-time Software Transactional Memory

Authors
Barros, A; Pinho, LM; Yomsi, PM;

Publication
JOURNAL OF SYSTEMS ARCHITECTURE

Abstract
Recent embedded processor architectures containing multiple heterogeneous cores and non-coherent caches renewed attention to the use of Software Transactional Memory (STM) as a building block for developing parallel applications. STM promises to ease concurrent and parallel software development, but relies on the possibility of abort conflicting transactions to maintain data consistency, which in turns affects the execution time of tasks carrying transactions. Because of this fact the timing behaviour of the task set may not be predictable, thus it is crucial to limit the execution time overheads resulting from aborts. In this paper we formalise a FIFO-based algorithm to order the sequence of commits of concurrent transactions. Then, we propose and evaluate two non-preemptive and one SRP-based fully-preemptive scheduling strategies, in order to avoid transaction starvation.

2015

Generalized Extraction of Real-Time Parameters for Homogeneous Synchronous Dataflow Graphs

Authors
Ali, HI; Akesson, B; Pinho, LM;

Publication
2015 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing

Abstract

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