Abstract

Abstract
The Network-on-Chip (NoC) architecture is an interconnect network with a good performance and scalability potential. Thus, it comes as no surprise that NoCs are among the most popular interconnect mediums in nowadays available many-core platforms. Over the years, the real-time community has been attempting to make NoCs amenable to the real-time analysis. One such approach advocates to employ virtual channels. Virtual channels are hardware resources that can be used as an infrastructure to facilitate flit-level preemptions between communication traffic flows. This gives the possibility to implement priority-preemptive arbitration policies in routers, which is a promising step towards deriving real-time guarantees for NoC traffic. So far, various aspects of priority-preemptive NoCs were studied, such as arbitration, priority assignment, routing, and workload mapping. Due to a potentially large solution space, the majority of available techniques are heuristic-centric, that is, either pure heuristics, or heuristic-based search strategies are used. Such approaches may lead to an inefficient use of hardware resources, and may cause a resource over-provisioning as well as unnecessarily high design-cost expenses. Motivated by this reality, we take a different approach, and propose an integer linear program to solve the problems of priority assignment and routing of NoC traffic. The proposed method finds optimal routes and priorities, but also allows to reduce the search space (and the computation time) by fixing either priorities or routes, and derive optimal values for remaining parameters. This framework is used to experimentally evaluate both the scalability of the proposed method, as well as the efficiency of existing priority assignment and routing techniques. © 2017 Springer Science+Business Media New York

Abstract
The use of parallel heterogeneous embedded architectures is needed to implement the level of performance required in advanced safety-critical systems. Hence, there is a demand for using high level parallel programming models capable of efficiently exploiting the performance opportunities. In this paper, we evaluate the incorporation of OpenMP, a parallel programming model used in HPC, into Ada, a language spread in safety-critical domains. We demonstrate that the execution model of OpenMP is compatible with the recently proposed Ada tasklet model, meant to exploit fine-grain structured parallelism. Moreover, we show the compatibility of the OpenMP and tasklet models, enabling the use of OpenMP directives in Ada to further exploit unstructured parallelism and heterogeneous computation. Finally, we state the safety properties of OpenMP and analyze the interoperability between the OpenMP and Ada runtimes. Overall, we conclude that OpenMP can be effectively incorporated into Ada without jeopardizing its safety properties.

Abstract
This chapter provides an overview of the book theme, motivating the need for high-performance and time-predictable embedded computing. It describes the challenges introduced by the need for time-predictability on the one hand, and high-performance on the other, discussing on a high level how these contradictory requirements can be simultaneously supported.

Abstract
Nowadays, the prevalence of computing systems in our lives is so ubiquitous that we live in a cyber-physical world dominated by computer systems, from pacemakers to cars and airplanes. These systems demand for more computational performance to process large amounts of data from multiple data sources with guaranteed processing times. Actuating outside of the required timing bounds may cause the failure of the system, being vital for systems like planes, cars, business monitoring, e-trading, etc. High-Performance and Time-Predictable Embedded Computing presents recent advances in software architecture and tools to support such complex systems, enabling the design of embedded computing devices which are able to deliver high-performance whilst guaranteeing the application required timing bounds. Technical topics discussed in the book include: Parallel embedded platforms, Programming models, Mapping and scheduling of parallel computations, Timing and schedulability analysis, Runtimes and operating systems. The work reflected in this book was done in the scope of the European project P SOCRATES, funded under the FP7 framework program of the European Commission. High-performance and time-predictable embedded computing is ideal for personnel in computer/communication/embedded industries as well as academic staff and master/research students in computer science, embedded systems, cyber-physical systems and internet-of-things.

Abstract