Abstract
The emergence of run-time reconfigurable architectures makes feasible the configure-execute paradigm. Compilation of behavioral descriptions (in, e.g., C, Java, etc.), apart from mapping the computational structures onto the available resources on the device, must split the program in temporal sections if it needs more resources than physically available. In addition, since the execution of the computational structures in a configuration needs at least two stages (i.e., configuring and computing), it is important to split the program such that the reconfiguration overheads are minimized, taking advantage of the overlapping of the execution stages on different configurations. This paper presents mapping techniques to cope with those features. The techniques are being researched in the context of a C compiler for the eXtreme Processing Platform (XPP). Temporal partitioning is applied to furnish a set of configurations that reduces the reconfiguration overhead and thus may lead to performance gains. We also show that when applications include a sequence of loops, the use of several configurations may be more beneficial than the mapping of the entire application onto a single configuration. Preliminary results for a number of benchmarks strongly confirm the approach.

Abstract
These techniques for compiling software programs into reconfigurable hardware offer faster and more efficient performance than the complex resource-sharing approaches typical of high-level synthesis systems. The Java-based compiler presented in this article uses intermediate graph representations to embody parallelism at various levels.

Abstract
Resource virtualization on FPGA devices, achievable due to its dynamic reconfiguration capabilities, provides an attractive solution to save silicon area. Architectural synthesis for dynamically reconfigurable FPGA-based digital systems needs to consider the case of reducing the number of temporal partitions (reconfigurations) by enabling sharing of some functional units in the same temporal partition. This paper proposes a novel algorithm for automated datapath design from behavioral input descriptions (represented by an acyclic dataflow graph), which simultaneously performs temporal partitioning and sharing of functional units. The proposed algorithm attempts to minimize both the number of temporal partitions and the execution latency of the generated solution. Temporal partitioning, resource sharing, scheduling, and a simple form of allocation and binding are all integrated in a single task. The algorithm is based on heuristics and on a new concept of construction by gradually enlarging timing slots. Results show the efficiency and effectiveness of the algorithm when compared to existent approaches.

Abstract
An increasing interest in the design of mobile robots has been observed in recent years, which is mainly motivated by technological advances that may allow their application to consumer markets, in addition to industrial areas. Although sophisticated techniques have been developed, choosing the appropriate hardware-software partitioning and programming robot functions are still very complex tasks. Current approaches often involve the design and implementation of hardwired solutions, with the associated problems of a long development cycle and inflexibility. In this paper we present a framework called ARCHITECT-R, which aims to design and program specialized hardware for robots based on FPGAs. We also present the first results obtained using this framework.

Abstract
This paper presents a technique, called loop dissevering, for temporally partitioning any type of loop presented in programming languages. The technique can be used in the presence of complex loops that oversize the physically available hardware resources. Unlike loop fission or distribution, the technique can be applied to all types of loops and it is not constrained by loop dependences. Thus, the technique guarantees the compilation of complex loops that otherwise cannot be mapped to the target reconfigurable computing architecture. Moreover, the technique only needs to communicate scalar variables between temporal partitions (configurations) and does not need auxiliary array variables used for scalar expansion when applying loop distribution. We show the results of applying the technique when compiling C programs to the PACT eXtreme Processing Platform (XPP) and to a hypothetical version with faster switching between contexts. We show that the technique leads to implementations using fewer resources and might lead to performance improvements when it is possible to overlap some of the execution stages (e.g., fetch, configure, and compute). As performance is concerned, the technique is most efficient and the reconfiguration time is fast. © 2003 IEEE.

Abstract
Peripheral nerve researchers frequently use the rat sciatic nerve crush model in order to test different therapeutic approaches. The purpose of this study was to determine the sequence of changes after an axonotmetic injury by means of a biomechanical model of the foot and ankle, and compare them with walking track analysis, over a fixed period of time. A kinematic analysis program was used to acquire ankle motion data for further analysis. Although repeated measures analysis of variance showed significant cumulative changes induced by the crush lesion for both ankle kinematic parameters and sciatic functional index, post-hoc multiple comparisons by the Student-Neuman-Keuls test revealed significant differences between week 0 and week 8 only for ankle kinematics. These results are of importance in showing the superiority of ankle kinematics in detecting small biomechanical deficits related to hyperexcitability of the plantarflexor muscles, in contrast with walking track analysis, which showed full motor functional recovery 8 weeks after the crush lesion.