Abstract
Over the years, many solutions have been suggested in order to improve object detection in maritime environments. However, none of these approaches uses flight information, such as altitude, camera angle, time of the day, and atmospheric conditions, to improve detection accuracy and network robustness, even though this information is often available and captured by the UAV. This work aims to develop a network unaffected by image-capturing conditions, such as altitude and angle. To achieve this, metadata was integrated into the neural network, and an adversarial learning training approach was employed. This was built on top of the YOLOv7, which is a state-of-the-art realtime object detector. To evaluate the effectiveness of this methodology, comprehensive experiments and analyses were conducted. Findings reveal that the improvements achieved by this approach are minimal when trying to create networks that generalize more across these specific domains. The YOLOv7 mosaic augmentation was identified as one potential responsible for this minimal impact because it also enhances the model's ability to become invariant to these image-capturing conditions. Another potential cause is the fact that the domains considered (altitude and angle) are not orthogonal with respect to their impact on captured images. Further experiments should be conducted using datasets that offer more diverse metadata, such as adverse weather and sea conditions, which may be more representative of real maritime surveillance conditions. The source code of this work is publicly available at https://git hub.com/ipleiria-robotics/maritime-metadata-adaptation.

Abstract

Abstract

Abstract
Advancements in semiconductor technology no longer occur at the pace the industry had been accustomed to. We have entered what is considered by many to be the post-Moore era. In order to continue scaling performance, increasingly heterogeneous architectures are being developed and the use of special purpose accelerators is on the rise. One notable example are Field-Programmable-Gate-Arrays (FPGAs), both in the data-center and embedded spaces. Advances in FPGA features and tools is allowing for critical kernels to be accelerated on specialized hardware without fabrication costs. However, re-targeting code to such heterogeneous platforms still requires significant refactoring of the compute intensive kernels, as well as knowledge of parallel compute and hardware design concepts for maximization of performance. We present Tribble, a source-to-source framework under active development, capable of transforming regular C/C++ programs for execution on heterogeneous architectures. This includes transforming the target kernel source code so that it is amenable for circuit generation while keeping the original version for software execution, inserting code for task and memory management and injecting a scheduler algorithm.

Abstract
A common approach for improving performance uses FPGAs to accelerate critical code regions, which often involves two processes: hardware/software partitioning, which identifies regions to offload to the FPGA; and optimizing those regions (e.g., through HLS directives). As both processes are separate and usually applied in sequence, the interplay between them is unnatural, and it is unclear how the choices made in one step can benefit the choices made in the other step. This paper presents our work-in-progress for combining partitioning and optimization into a single holistic process. First, our source-to-source compiler builds a task-based representation from the input application. Then, a greedy algorithm builds clusters of tasks and assigns each cluster to either hardware (FPGA) or software (CPU). The algorithm iteratively refines the clusters and offloading decisions by: a) minimizing the communication costs between clusters by assigning tasks that work with shared data to the same cluster; b) reducing the global execution time by applying code optimizations to the tasks in each cluster. We show the impact of our holistic approach to a motivating edge detection example and compare the results when applying partitioning and code optimizations as independent steps. The results show that a holistic partitioning can lead to a speedup of up to 28.7x when compared to a simple offloading of the application to an FPGA.

Abstract
This work addresses the contemporary challenges in computing, caused by the stagnation of Moore's Law and Dennard scaling. The shift towards heterogeneous architectures necessitates innovative compilation strategies, prompting initiatives like the Multi-Level Intermediate Representation (MLIR) project, where progressive code lowering can be achieved through the use of dialects. Our work focuses on developing an MLIR dialect capable of representing streaming data accesses to memory, and Single Instruction Multiple Data (SIMD) vector operations. We also propose our own Structured Representation Language (SRL), a Design Specific Language (DSL) to serve as a precursor into the MLIR layer and subsequent inter-operation between new and existing dialects. The SRL exposes the streaming and vector computational concepts to a higher-level, and serves as intermediate step to supporting code generation containing our proposed dialect from arbitrary input code, which we leave as future work. This paper presents the syntaxes of the SRL DSL and of the dialect, and illustrates how we aim to employ them to target both General-Purpose Processors (GPPs) with SIMD co-processors and custom hardware options such as Field-Programmable Gate Arrayss (FPGAs) and Coarse-Grained Re-configurable Arrays (CGRAs).