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Sobre

Sobre

João M. P. Cardoso obteve o grau de Doutor em Engenharia Electrotécnica e Computadores no IST/UTL (Instituto Superior Técnico/Universidade Técnica de Lisboa), Lisboa, Portugal, em 2001. É actualmente Professor Catedrático no Departamento de Engenharia Informática (DEI) da Faculdade de Engenharia da Universidade do Porto (FEUP) e investigador sénior no INESC TEC. Previamente, ele foi Prof. Auxiliar no IST/UTL (2006-2008), investigador sénior no INESC-ID (2001-2009), e Prof. Auxiliar na Universidade do Algarve (1993-2006). Em 2001/2002, trabalhou na PACT XPP Technologies, Inc., em Munique, Alemanha. Tem estado envolvido na organização e tem servido como membro do comité científico de muitas conferências internacionais. Por exemplo, foi General Co-Chair da IEEE/IFIP EUC’2015 e da IEEE CSE’2015, General Chair da FPL’2013, General Co-Chair da ARC’2014 e ARC’2006, Program Co-Chair da ARCS’2016, DASIP’2014, e RAW’2010. É co-autor de mais de 150 publicações científicas em tópicos relacionados com compiladores, sistemas embebidos, e computação reconfigurável. Coordenou vários projectos de investigação. É um membro sénior do IEEE e do ACM e membro da IEEE Computer Society. Os seus interesses de investigação incluem técnicas de compiladores, linguages específicas ao domínio, computação reconfigurável, arquitecturas específicas à aplicação, e computação de elevado desempenho com ênfase em computação embebida.

Tópicos
de interesse
Detalhes

Detalhes

  • Nome

    João Paiva Cardoso
  • Cargo

    Investigador Sénior
  • Desde

    01 julho 2011
  • Nacionalidade

    Portugal
  • Contactos

    +351222094199
    joao.paiva.cardoso@inesctec.pt
002
Publicações

2023

Electrical sensing of the plant Mimosa pudica under environmental temperatures

Autores
Lobo, MA; Cardoso, JMP; Rocha, PRF;

Publicação
2023 IEEE 7TH PORTUGUESE MEETING ON BIOENGINEERING, ENBENG

Abstract
Plants gather and process information about their surroundings to make decisions that prioritize their well-being while considering the environment. These decisions are conveyed through electrical signals within and between cells, mainly in the form of action and variation potentials, in response to stimuli, including mechanical vibrations, changes in temperature, light intensity, and humidity. Although the ability of some plants, such as the Mimosa pudica, to react to sudden environmental stimuli (e.g., touch) is well known, their long-term electrical response under slow environmental changes remains not fully understood. Here, a multi-source monitoring system has been developed to collect and store electrical signals from the plant Mimosa pudica, and surrounding environmental temperature and humidity, over a period of approximately 5 days. A realtime dashboard shows the environmental temperature and variation potential (VP) from Mimosa pudica. The VP mimics the environmental temperature changes, with an associated delay. Our long-term physiological observations suggest that environmental temperature sensing in the plant Mimosa pudica can be monitored and is likely driven by bioelectricity.

2023

A Study on Hyperparameters Configurations for an Efficient Human Activity Recognition System

Autores
Ferreira, PJS; Mendes-Moreira, J; Cardoso, JMP;

Publicação
PROCEEDINGS OF THE 8TH INTERNATIONAL WORKSHOP ON SENSOR-BASED ACTIVITY RECOGNITION AND ARTIFICIAL INTELLIGENCE, IWOAR 2023

Abstract
Human Activity Recognition (HAR) has been a popular research field due to the widespread of devices with sensors and computational power (e.g., smartphones and smartwatches). Applications for HAR systems have been extensively researched in recent literature, mainly due to the benefits of improving quality of life in areas like health and fitness monitoring. However, since persons have different motion patterns when performing physical activities, a HAR system would need to adapt to the characteristics of the user in order to maintain or improve accuracy. Mobile devices, such as smartphones, used to implement HAR systems, have limited resources (e.g., battery life). They also have difficulty adapting to the device's constraints to work efficiently for long periods. In this work, we present a kNN-based HAR system and an extensive study of the influence of hyperparameters (window size, overlap, distance function, and the value of k) and parameters (sampling frequency) on the system accuracy, energy consumption, and response time. We also study how hyperparameter configurations affect the model's performance for the users and the activities. Experimental results show that adapting the hyperparameters makes it possible to adjust the system's behavior to the user, the device, and the target service. These results motivate the development of a HAR system capable of automatically adapting the hyperparameters for the user, the device, and the service.

2023

A DSL-based runtime adaptivity framework for Java

Autores
Carvalho, T; Bispo, J; Pinto, P; Cardoso, JMP;

Publicação
SOFTWAREX

Abstract
This article presents Kadabra, a Java source-to-source compiler that allows users to make code queries, code analysis and code transformations, all user-programmable using the domain-specific language LARA. We show how Kadabra can be used as the basis for developing a runtime autotuning and adaptivity framework, able to adapt existing source Java code in order to take advantage of runtime autotuning. Specifically, this article presents the framework, consisting of Kadabra and an API for runtime adaptivity. We show the use of the framework to extend Java applications with autotuning and runtime adaptivity mechanisms to target performance improvement and/or energy saving goals.(c) 2023 The Authors. Published by Elsevier B.V. This is an open access article under the CC BY license (http://creativecommons.org/licenses/by/4.0/).

2023

Preface ASAP 2023

Autores
Cardoso, JMP; Jimborean, A; Mentens, N; Coutinho, JGF;

Publicação
34th IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2023, Porto, Portugal, July 19-21, 2023

Abstract
[No abstract available]

2023

A CPU-FPGA Holistic Source-To-Source Compilation Approach for Partitioning and Optimizing C/C plus plus Applications

Autores
Santos, T; Bispo, J; Cardoso, JMP;

Publicação
2023 32ND INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES, PACT

Abstract
A common approach for improving performance uses FPGAs to accelerate critical code regions, which often involves two processes: hardware/software partitioning, which identifies regions to offload to the FPGA; and optimizing those regions (e.g., through HLS directives). As both processes are separate and usually applied in sequence, the interplay between them is unnatural, and it is unclear how the choices made in one step can benefit the choices made in the other step. This paper presents our work-in-progress for combining partitioning and optimization into a single holistic process. First, our source-to-source compiler builds a task-based representation from the input application. Then, a greedy algorithm builds clusters of tasks and assigns each cluster to either hardware (FPGA) or software (CPU). The algorithm iteratively refines the clusters and offloading decisions by: a) minimizing the communication costs between clusters by assigning tasks that work with shared data to the same cluster; b) reducing the global execution time by applying code optimizations to the tasks in each cluster. We show the impact of our holistic approach to a motivating edge detection example and compare the results when applying partitioning and code optimizations as independent steps. The results show that a holistic partitioning can lead to a speedup of up to 28.7x when compared to a simple offloading of the application to an FPGA.

Teses
supervisionadas

2023

Source-to-source Programmable Performance Engineering For High-Performance Computing

Autor
Pedro Miguel dos Santos Pinto

Instituição
UP-FEUP

2023

Enhancing Forecasting using Read & Write Recurrent Neural Networks

Autor
Yassine Baghoussi

Instituição
UP-FEUP

2023

FPGA-based kNN Accelerators via High-Level Synthesis

Autor
André Filipe Ferreira da Silva

Instituição
UP-FEUP

2023

Energy-Computing Efficient Classification Techniques for Mobile-Based HAR Systems

Autor
Paulo Jorge Silva Ferreira

Instituição
UP-FEUP

2023

Code Specialization for Targeting FPGAs via High-Level Synthesis Tools

Autor
Vitória Alexa Maciel Correia

Instituição
UP-FEUP