Abstract
In this work, both analogue and digital depletionmode single channel transistor circuits are presented and are simulated using an n-channel IGZO technology with V-TH =-0.87V. A logic family is introduced, suppressing the need for an additional voltage level and level restoring circuitry. Furthermore, in the analogue domain, a depletion current mirror topology is presented with demonstrated small current error. Finally, the current mirror is used in the design of an OpAmp, achieving a simulated open-loop gain of 45 dB, CMRR of 58 dB, unity-gain frequency of 444 kHz and a phase margin of 71 degrees.

Abstract
This study explores the resistive switching phenomena present in 4 mu m(2) amorphous Indium-Gallium-Zinc Oxide (IGZO) memristors. Despite being extensively reported in the literature, not many studies detail the mechanisms that dominate conduction on the different states of IGZO-based devices. In this article, we demonstrate that resistive switching occurs due to the modulation of the Schottky barrier present at the bottom interface of the device. Furthermore, thermionic field emission and field emission regimes are identified as the dominant conduction mechanisms at the high resistive state of the device, while the bulk-limited ohmic conduction is found at the low resistive state. Due to the high complexity associated with creating compact models of resistive switching, a data-driven model is drafted taking systematic steps. (C) 2022 Author(s).

Abstract
Memristor crossbar arrays can compose the efficient hardware for artificial intelligent applications. However, the requirements for a linear and symmetric synaptic weight update and low cycle-to-cycle (C2C) and device-to-device variability as well as the sneak-path current issue have been delaying its further development. This study reports on a thin-film amorphous oxide-based 4x4 1-transistor 1-memristor (1T1M) crossbar. The a-IGZO crossbar is built on a flexible polyimide substrate, enabling IoT and wearable applications. In the novel framework, the thin-film transistor and memristor are fabricated at the same level, with the same processing steps and sharing the same materials for all layers. The 1T1M cells show linear and symmetrical plasticity characteristic with low C2C variability. The memristor performs like an analog dot product engine and vector-matrix multiplications in the 4x4 crossbars is demonstrated experimentally, in which the sneak-path current issue is successfully suppressed, resulting in a proof-of-concept for a cost-effective, flexible artificial neural networks hardware.

Abstract
In this paper, the most suited analog-to-digital (A/D) converters (ADCs) for Internet of Things (IoT) applications are compared in terms of complexity, dynamic performance, and energy efficiency. Among them, an innovative hybrid topology, a digital-delta (& UDelta;) modulator (& UDelta;M) ADC employing noise shaping (NS), is proposed. To implement the active building blocks, several standard-cell-based synthesizable comparators and amplifiers are examined and compared in terms of their key performance parameters. The simulation results of a fully synthesizable Digital-& UDelta;M with NS using passive and standard-cell-based circuitry show a peak of 72.5 dB in the signal-to-noise and distortion ratio (SNDR) for a 113 kHz input signal and 1 MHz bandwidth (BW). The estimated FoMWalden is close to 16.2 fJ/conv.-step.

Abstract
Resistive switching behaviour has been demonstrated to be a common characteristic to many materials. In this regard, research teams to date have produced a plethora of different devices exhibiting diverse behaviour, but when system design is considered, finding a 'one-model-fits-all' solution can be quite difficult, or even impossible. However, it is in the interest of the community to achieve more general modelling tools for design that allows a quick model update as devices evolve. Laying the grounds with such a principle, this paper presents an artificial neural network learning approach to resistive switching modelling. The efficacy of the method is demonstrated firstly with two simulated devices and secondly with a 4 mu m(2) amorphous IGZO device. For the amorphous IGZO device, a normalized root-mean-squared error (NRMSE) of 5.66 x 10(-3) is achieved with a [2, 50,50 ,1] network structure, representing a good balance between model complexity and accuracy. A brief study on the number of hidden layers and neurons and its effect on network performance is also conducted with the best NRMSE reported at 4.63 x 10(-3). The low error rate achieved in both simulated and real-world devices is a good indicator that the presented approach is flexible and can suit multiple device types.