Abstract
As the number of wireless devices, services, communication standards and respective modes of operation rapidly grows, the design of reconfigurable digital baseband processing systems for radio devices becomes more important and challenging. Long Term Evolution (LTE) is among the most relevant wireless systems in 4G communications and its waveform is OFDM-based. According to the LTE mode of operation, OFDM parameters may change and influence baseband processing operations. This paper presents a dynamically reconfigurable LTE-compliant OFDM modulator for Downlink transmission able to adapt its internal hardware organization on-demand according to the digital modulation scheme and OFDM parameters, such as number of data subcarriers, IFFT size, Cyclic Prefix and window length. System reconfiguration is performed by employing FPGA-based Dynamic Partial Reconfiguration (DPR) techniques. The worst-case DPR latencies measured are 895 mu s and 1.192 ms for digital modulation and channel bandwidth adaptation, respectively. These results show that the adopted design approach is feasible in wireless baseband processing systems. Power estimations suggest that circuit specialization at run-time can potentially improve system power efficiency.

Abstract
Cognitive Radios (CR) are viewed as a solution for spectrum utilization and management in next generation wireless networks. In order to adapt themselves to the actual communications environment, CR devices require highly flexible baseband processing engines. One of the most relevant operations involved in radio baseband processing is the FFT. This work presents a reconfigurable FFT processor supporting FFT sizes and throughputs required by the most used wireless communication standards. By employing Dynamic Partial Reconfiguration (DPR), the implemented design can adapt the FFT size at run-time and specialize its operation to the immediate communication demands. This translates to hardware savings, enhanced resource usage efficiency and possible power savings. The results obtained for reconfiguration times suggest that DPR techniques are a viable option for designing flexible and adaptable baseband processing components for CR devices. © Springer International Publishing Switzerland 2016.

Abstract
This paper proposes a new open-loop and low complexity (small size) fast-lock synchronization circuit for clock and data recovery in wearable systems. The system includes sensors embedded in textile and connected by conductive yarns. Synchronization is based on the open-loop selection of the correct phase of the receiver clock synchronously with the incoming signal. The clock generator of the receiver is an autonomous oscillator set to operate at the same nominal frequency. The circuit lock time is at most one clock cycle, faster than all methods based on phase-locked loops or delay-locked loops. The circuit can be used for baseband communication independently of the signal coding method used in the physical layer, making it suitable for many applications. The fully digital circuit (including non-return-to-zero inverted decoder) occupies 0.0022 in a 0.35 complementary metal-oxide semiconductor (CMOS) process, a smaller implementation than many existing circuits, and supports a maximum system clock frequency of 70 for a 35-data rate. Experimental results demonstrate that the proposed circuit robustly generates a synchronous clock for data recovery. The circuit is suitable for systems that tolerate some jitter but requires fast lock time, small size, and low energy consumption. Copyright (c) 2015 John Wiley & Sons, Ltd.

Abstract
Our work proposes a hardware architecture for a Long Short-Term Memory (LSTM) Neural Network, aiming to outperform software implementations, by exploiting its inherent parallelism. The main design decisions are presented, along with the proposed network architecture. A description of the main building blocks of the network is also presented. The network is synthesized for various sizes and platforms, and the performance results are presented and analyzed. Our synthesized network achieves a 251 times speed-up over a custom-built software network, running on an i7-3770k Desktop computer, proving the benefits of parallel computation for this kind of network.

Abstract
In this paper we address the transformation of whispered speech into natural voiced speech. Representative state-of-the-art solutions are first reviewed as well as a baseline algorithm. For the most part, these solutions fall in the realm of voice conversion strategies since the output signal is obtained as a projection of an input signal. In this paper, we propose a different approach that addresses flexible parametric synthesis of the voiced signal component, as well as its implantation on the whispered signal, in a linguistically consistent way and while trying to convey idiosyncratic information. The most critical functions of phonetic segmentation, spectral envelope estimation, arbitrary periodic wave shape synthesis, and F0 modulation, are described and their operation illustrated with examples.

Abstract
In recent years, tools in perceptual coding of high-quality audio have been tailored to capture highly detailed information regarding signal components so that they gained an intrinsic ability to represent audio parametrically. In a recent paper, we described a first validation model to such an approach applied to parametric coding of wideband speech. In this paper we describe specific advances to such an approach that improve coding efficiency and signal quality. A special focus is devoted to the fact that persistent transmission to the decoder of phase information is avoided, to the synthesis of both impulse-like and noise-based plosives using short-term windows, to improved ways of spectral envelope modelling, and to the fact that direct synthesis in the time-domain of the periodic content of speech is allowed in order to cope with fast F0 changes. A few examples of signal coding and transformation illustrate the impact of those improvements.