Abstract
Statistics show an aging trend in the world population, which will progressively overload existing health systems. Therefore, we believe that ubiquitous computing will play an important role in domicile settings, coping with the growing need for automated home healthcare support, especially for the sick and elderly. The integration of independently developed off-the-shelf systems (e.g., health-monitoring, entertainment, communications, home automation, etc.) may cause unplanned interactions between them (cf. feature interactions). This is a major concern since the correct/expected behavior of an isolated system may not be the same when deployed in conjunction with other systems, causing interferences, i.e., unexpected outcomes or misbehaviors. The Safe Home Care project tackles this problem to pursuit the safe deployment and reconfiguration of home healthcare smart-spaces. We propose the use of state graphs to represent off-the-shelf systems and predict the occurrence of intra-system's feature interactions. We use pre-deployment simulations to forecast feature interactions before deployment. We assess the applicability and correctness of this approach through a set of simulated home assisted living scenarios. © 2012 IEEE.

Abstract
Off-the-shelf smart devices and applications are expected to be pivotal in the coming need for massive home care. Deployment and integration of these systems in the same household may result in unplanned interactions involving users and entertainment, communication, and health-related devices. These unplanned interactions are a major concern when, for example, communication or entertainment applications interfere with the behavior of health-related devices. This paper presents a novel graph-based approach for representing the expected behavior of off-the-shelf smart devices and applications, their interactions, and for detecting interference in home care settings. A set of home care scenarios is used to assess the applicability of our approach. Our graph-based interference detection approach is integrated in the Safe Home Care reflective platform, which allows reifying the state of off-the-shelf systems and simulating home care scenarios. © 2012 IEEE.

Abstract
This work addresses a built-in self-test methodology for circuit cell identification under specific matching conditions. The proposed technique is applied to the CMOS realization of a reduced-KII network, which is a system model of the biological olfactory cortex. This model behaves as an associative memory, a useful tool for information and adaptive processes. Based on a mixed-signal approach, the test strategy makes proper use of the circuits comprising the network structure, and provides self reconfiguration as well. Both testing procedures and design of essential building blocks are described in this paper. Simulation results are presented for a reduced-KII network comprising 128-cells, sequentially tested for matching in terms of offsets and their dynamic performances.

Abstract
This paper presents two initiatives run by groups of engineering students at the University of Porto: the Microelectronics Students' Group and BioStar. These groups are student-led initiatives that promote different scientific fields through self-guided projects. Both experiences have proven to be very successful in increasing the undergraduate student's interest in science and technology. This work reports the activities, organization and main methodologies employed by these groups, which can be seen as successful approaches to enhance the technical curriculum of students. © 2012 IEEE.

Abstract
This paper presents the results of a preliminary study to examine the ability of post-silicon devices for analog processing. It is focused on the latest thin-film transistors (TFTs) with amorphous gallium-indium-zinc oxide (a-GIZO) as active layer. Three circuit configurations are presented: a differential pair and two multiplier topologies. Both triode and saturation regions of operation are included in the analysis, with the devices set to remain in strong accumulation. A neural model, which is developed based on the measured data of the TFTs, is used for the circuit simulations in the Cadence Virtuoso environment. The analog multipliers simulation results are compared against the expected functional results.

Abstract
This paper addresses a modeling and simulation methodology for analog circuit design with amorphous-GIZO thin-film transistors (TFTs). To reach an effective circuit design flow, with commercially available tools, a TFT model has been first developed with an artificial neural network (ANN). Multilayer perceptron with backpropagation algorithm has been adopted to model the static behavior of the TFT devices, for different aspect ratios. The model was then implemented in Verilog-A, to allow a quick instantiation in circuit. Simulations using Cadence Spectre are performed to validate the model. On a second phase, simulation results of basic analog circuits, with this ANN model, are verified against the actual functional results, namely an adder, subtractor, and current mirror circuit. Results demonstrate not only the ANN model accuracy and compatibility with dc and transient analysis, but also show the a-GIZO TFT capability to perform analog operations. © 2012 IEEE.