Abstract
As applications move to the edge, efficiency in computing power and power/energy consumption is required. Heterogeneous computing promises to meet these requirements through application-specific hardware accelerators. Runtime adaptivity might be of paramount importance to realize the potential of hardware specialization, but further study is required on workload retargeting and offloading to reconfigurable hardware. This article presents our framework for the exploration of both offloading and hardware generation techniques. The framework is currently able to process instruction sequences from MicroBlaze, ARMv8, and riscv32imaf binaries, and to represent them as Control and Dataflow Graphs for transformation to implementations of hardware modules. We illustrate the framework's capabilities for identifying binary sequences for hardware translation with a set of 13 benchmarks.

Abstract
The 2019/2020 school year will always be remembered for the impact of the COVID-19 pandemic. For the first time in recent history, countries closed schools and forced instructors and students to quickly adjust to online classes. This sudden and forced shift to a method of teaching that was completely different from what we were used to presented several challenges and opportunities on a pedagogical level. In this paper we describe our experience as instructors in a course on microprocessor programming in the Master's Degree in Computer Science and Computing Engineering at the Faculty of Engineering of the University of Porto. Our approach included changes to the assessment plan, which became more distributed, and improvements in communication between students and instructors through the use of Slack. We found that the changes introduced were not only very well received by students, but also resulted in the best exam attendance and average final grade in the last 10 years of the course's history.

Abstract
By using Dynamic Binary Translation, instruction traces from pre-compiled applications can be offloaded, at runtime, to FPGA-based accelerators, such as Coarse-Grained Loop Accelerators, in a transparent way. However, scheduling onto coarse-grain accelerators is challenging, with two of current known issues being the density of computations that can be mapped, and the effects of memory accesses on performance. Using an in-house framework for analysis of instruction traces, we explore the effect of different window sizes when applying list scheduling, to map the window operations to a coarse-grain loop accelerator model that has been previously experimentally validated. For all window sizes, we vary the number of ALUs and memory ports available in the model, and comment how these parameters affect the resulting latency. For a set of benchmarks taken from the PolyBench suite, compiled for the 32-bit MicroBlaze softcore, we have achieved an average iteration speedup of 5.10x for a basic block repeated 5 times and scheduled with 8 ALUs and memory ports, and an average speedup of 5.46x when not considering resource constraints. We also identify which benchmarks contribute to the difference between these two speedups, and breakdown their limiting factors. Finally, we reflect on the impact memory dependencies have on scheduling.

Abstract
Whispered-voice to normal-voice conversion is typically achieved using codec-based analysis and re-synthesis, using statistical conversion of important spectral and prosodic features, or using data-driven end-to-end signal conversion. These approaches are however highly constrained by the architecture of the codec, the statistical projection, or the size and quality of the training data. In this paper, we presume direct implantation of voiced phonemes in whispered speech and we focus on fully flexible parametric models that i) can be independently controlled, ii) synthesize natural and linguistically correct voiced phonemes, iii) preserve idiosyncratic characteristics of a given speaker, and iv) are amenable to co-articulation effects through simple model interpolation. We use natural spoken and sung vowels to illustrate these capabilities in a signal modeling and re-synthesis process where spectral magnitude, phase structure, F-0 contour and sound morphing can be independently controlled in arbitrary ways.

Abstract
The ability to operate virtually anywhere and carry payload makes Unmanned Aerial Vehicles (UAVs) perfect platforms to carry communications nodes, including Wi-Fi Access Points (APs) and cellular Base Stations (BSs). This is paving the way to the deployment of flying networks that enable communications to ground users on demand. Still, flying networks impose significant challenges in order to meet the Quality of Experience expectations. State of the art works addressed these challenges, but have been focused on routing and the placement of the UAVs as APs and BSs serving the ground users, overlooking the backhaul network design. The main contribution of this paper is a centralized traffic-aware Gateway UAV Placement (GWP) algorithm for flying networks with controlled topology. GWP takes advantage of the knowledge of the offered traffic and the future topologies of the flying network to enable backhaul communications paths with high enough capacity. The performance achieved using the GWP algorithm is evaluated using ns-3 simulations. The obtained results demonstrate significant gains regarding aggregate throughput and delay.

Abstract
The ability to operate anywhere, anytime, as well as their capability to hover and carry cargo on board make Unmanned Aerial Vehicles (UAVs) suitable platforms to act as Flying Gateways (FGWs) to the Internet. The problem is the optimal placement of the FGWs within the flying network, such that the Quality of Service (QoS) offered is maximized. The literature has been focused on optimizing the placement of the Flying Access Points (FAPs), which establish high-capacity small cells to serve the users on the ground, overlooking the backhaul network design, including the FGW placement. The FGW placement problem is exacerbated in highly dynamic flying networks, where the dynamic traffic demand and the movements of the users may induce frequent changes in the placement of the FAPs. The main contribution of this paper is a fast gateway placement (F-GWP) algorithm for flying networks that determines the optimal position of a FGW. With F-GWP, backhaul communications paths with high enough capacity are established between the FAPs and the FGW, in order to accommodate the traffic demand of the users on the ground. Simulation and experimental results show F-GWP is two orders of magnitude faster than its state of the art counterpart, while ensuring the same flying network performance.