Abstract
The overtaking maneuver can be often dangerous and risky, especially when driving in rural roads, with a significant probability of leading to fatalities and serious injuries. Vehicle communication emerges as one of the leading technologies to improve the driving experience and road safety. This article presents a system designed to augment road safety in an Overtaking Maneuver, providing the ahead vehicle's Line-of-Sight by real-time video-streaming. It uses the C-V2X Transmission Mode 4 that, building upon cellular technology, has evolved as one of the main standards for vehicle communication. Results show an effective application of the system in real overtaking scenarios, enhancing the safety and proving its usefulness. Whilst having some impact on the latency, the solution incurred in low packet losses and provided good video quality.

Abstract
Mobile Augmented Reality (MAR) systems have emerged and greatly evolved in the last two decades. They have application in many domains, most notably in the field of Cultural Heritage (CH) and tourism, where people tend to rely on smartphones when visiting a new city to obtain additional information on the city landmarks. Expectations are that they obtain precise and tailored information to the visitor’s needs. Therefore, researchers started to investigate innovative approaches for presenting and suggesting digital content related to cultural and historical places. This article presents a novel MAR application, NearHeritage, which uses emergent technologies to assist visitors in finding and exploring Cultural Heritage. The research focuses on combining the use of context-awareness with Augmented Reality (AR). By sensing the context surrounding the user, the NearHeritage app discloses not only the list of nearby points-of-interest (POI) but also detailed information about the POIs in the form of AR content adapted to the user context. The solution presented uses built-in sensors of Android devices and takes advantage of various APIs (Foursquare API, Google Maps API and IntelContextSensing SDK) to retrieve information about the landmarks and the visitor context. Results from initial experimentation indicate that the concept of a context-aware MAR application can improve the user experience in discovering and learning more about Cultural Heritage, creating an interactive, enjoyable and unforgettable adventure. © 2021, The Author(s), under exclusive license to Springer Nature Switzerland AG.

Abstract
In future wireless communication systems, several radio access technologies will coexist and interwork to provide a great variety of services with different requirements. Thus, the design of flexible and reconfigurable hardware is a relevant topic in wireless communications. The combination of high performance, programmability and flexibility makes Field-programmable gate array a convenient platform to design such systems, especially for base stations. This paper describes a dynamically reconfigurable baseband modulator for Orthogonal Frequency Division Multiplexing and Filter-bank Multicarrier modulation waveforms implemented on a Virtex-7 board. The design features Dynamic Partial Reconfiguration (DPR) capabilities to adapt its mode of operation at run-time and is compared with a functionally equivalent static multi-mode design regarding processing throughput, resource utilization, functional density and power consumption. The DPR-based design implementation reserves about half the resources used by static multi-mode counterpart. Consequently, the baseband processing dynamic power consumption observed in the DPR-based design is between 26 mW to 90 mW lower than in the static multi-mode design, representing a dynamic power reduction between 13% to 52%. The worst-case DPR latency measured was 1.051 ms, while the DPR energy overhead is below 1.5 mJ. Considering latency requirements for modern wireless standards and power consumption constraints for commercial base stations, the DPR application is shown to be valuable in multi-standard and multi-mode systems, as well as in scenarios such as multiple-input and multiple-output or dynamic spectrum aggregation.

Abstract
The K-means algorithm is widely used to find correlations between data in different application domains. However, given the massive amount of data stored, known as Big Data, the need for high-speed processing to analyze data has become even more critical, especially for real-time applications. A solution that has been adopted to increase the processing speed is the use of parallel implementations on FPGA, which has proved to be more efficient than sequential systems. Hence, this paper proposes a fully parallel implementation of the K-means algorithm on FPGA to optimize the system & x2019;s processing time, thus enabling real-time applications. This proposal, unlike most implementations proposed in the literature, even parallel ones, do not have sequential steps, a limiting factor of processing speed. Results related to processing time (or throughput) and FPGA area occupancy (or hardware resources) were analyzed for different parameters, reaching performances higher than 53 millions of data points processed per second. Comparisons to the state of the art are also presented, showing speedups of more than over a partially serial implementation.

Abstract
The breakdown of Dennard scaling has resulted in a decade-long stall of the maximum operating clock frequencies of processors. To mitigate this issue, computing shifted to multi-core devices. This introduced the need for programming flows and tools that facilitate the expression of workload parallelism at high abstraction levels. However, not all workloads are easily parallelizable, and the minor improvements to processor cores have not significantly increased single-threaded performance. Simultaneously, Instruction Level Parallelism in applications is considerably underexplored. This article reviews notable approaches that focus on exploiting this potential parallelism via automatic generation of specialized hardware from binary code. Although research on this topic spans over more than 20 years, automatic acceleration of software via translation to hardware has gained new importance with the recent trend toward reconfigurable heterogeneous platforms. We characterize this kind of binary acceleration approach and the accelerator architectures on which it relies. We summarize notable state-of-the-art approaches individually and present a taxonomy and comparison. Performance gains from 2.6x to 5.6x are reported, mostly considering bare-metal embedded applications, along with power consumption reductions between 1.3x and 3.9x. We believe the methodologies and results achievable by automatic hardware generation approaches are promising in the context of emergent reconfigurable devices.

Abstract
A multifunctional router IC to be included in the nodes of a wearable body sensor network is described and evaluated. The router targets different application scenarios, especially those including tens of sensors, embedded into textile materials and with high data-rate communication demands. The router IC supports two different functionality sets, one for sensor nodes and another for the base node, both based on the same circuit module. The nodes are connected to each other by means of woven thick conductive yarns forming a mesh topology with the base node at the center. From the standpoint of the network, each sensor node is a four port router capable of handling packets from destination nodes to the base node, with sufficient redundant paths. The adopted hybrid circuit and packet switching scheme significantly improve network performance in terms of end-to-end delay, throughput and power consumption. The IC also implements a highly precise, sub-microsecond one-way time synchronization protocol which is used for time stamping the acquired data. The communication module was implemented in a 4-metal, 0.35 mu m CMOS technology. The maximum data rate of the system is 35 Mbps while supporting up to 250 sensors, which exceeds current BAN applications scenarios.