Abstract
A novel linear analog adder is proposed only with n-type enhancement IGZO TFTs that computes summation of four voltage signals. However, this design can be easily extended to perform summation of higher number of signals, just by adding a single TFT for each additional signal in the input block. The circuit needs few number of transistors, only a single power supply irrespective of the number of voltage signals to be added, and offers good accuracy over a reasonable range of input values. The circuit was fabricated on glass substrate with the annealing temperature not exceeding 200 degrees C. The circuit performance is characterized from measurements under normal ambient at room temperature, with a power supply voltage of 12 V and a load of approximate to 4pF. The designed circuit has shown a linearity error of 2.3% (until input signal peak to peak value is 2 V), a power consumption of 78 mu W and a bandwidth of approximate to 115 kHz, under the worst case condition (when it is adding four signals with the same frequency). In this test setup, it has been noticed that the second harmonic is 32 dB below the fundamental frequency component. This circuit could offer an economic alternative to the conventional approaches, being an important contribution to increase the functionality of large area flexible electronics.

Abstract
IEEE 1687 standard (IJTAG), as an extension to the IEEE 1149.1, facilitates efficient access to embedded instruments by supporting reconfigurable scan networks. Specifically, IJTAG allows each IP to be wrapped by a test data register (TDR) whose access is controlled by a segment insertion bit (SIB) or a scan-mux control bit (SCB). Because the TDRs and the SIB/SCB network are typically not public, but critical for accessing embedded instruments, they might be used for illegitimate purposes, such as dumping credential data and reverse engineering IP design. Machine learning has been proposed to detect such attacks, but the large number of instruments and parallel execution enabled by the IJTAG produce high-dimensional data, which poses a challenge to on-chip detection. In this paper, we propose to reduce the high-dimensional but sparse data using a low-density parity-check (LDPC) matrix. Experiments using a modified version of the OpenSPARC T2 to include IJTAG functionality demonstrate that the use of feature reduction eliminates 91% of the features, leading to 43% reduction in circuit size without affecting detection accuracy. Also, the on-chip detector adds moderate overhead (similar to 8%) to the IJTAG.

Abstract
This paper presents a novel high-gain transimpedance amplifier for flexible radiation sensing systems that can be used as large-area dosimeters. The circuit is implemented with indium-gallium-zinc-oxide thin-film-transistors and uses two stages for the amplification of the sensor signal (current). The first stage consists of cascode current mirrors with a diode connected load that performs current amplification and voltage conversion. Then, the first stage is followed by a voltage amplifier based on a positive feedback topology for gain enhancement. The proposed circuit converts nano-ampere (10 nA) currents into hundreds of millivolts (280 mV), showing a gain around 149 dB and a power consumption of 0.45 mW. The sensed radiation dose level, in voltage terms, can drive the next stages in the radiation sensing system, such as analog to digital converters. These radiation sensing devices can find potential applications in real-time, large area, flexible health, and security systems.

Abstract
Sparse coding techniques have seen an increasing range of applications in recent years, especially in the area of image processing. In particular, sparse coding using l(1)-regularization has been efficiently solved with the Augmented Lagrangian (AL) applied to its dual formulation (DALM). This paper proposes the decomposition of the dictionary matrix in its Singular Value/Vector form in order to simplify and speed-up the implementation of the DALM algorithm. Furthermore, we propose an update rule for the penalty parameter used in AL methods that improves the convergence rate. The SVD of the dictionary matrix is done as a pre-processing step prior to the sparse coding, and thus the method is better suited for applications where the same dictionary is reused for several sparse recovery steps, such as block image processing.

Abstract
In this paper, we adopt a novel numerical algorithm, referred to as dual augmented Lagrangian method (DALM), for efficient test cost reduction based on spatial variation modeling. The key idea of DALM is to derive the dual formulation of the L-1-regularized least-squares problem posed by Virtual Probe (VP), which can be efficiently solved with substantially lower computational cost than its primal formulation. In addition, a number of unique properties associated with discrete cosine transform (DCT) are exploited to further reduce the computational cost of DALM. Our experimental results of an industrial RF transceiver demonstrate that the proposed DALM solver achieves up to 38 runtime speed-up over the conventional interior-point solver without sacrificing any performance on escape rate and yield loss for test applications.

Abstract
This paper presents a high speed digitally programmable Ring Oscillator (RO) using Indium-galliumzinc oxide thin-film transistors (IGZO TFTs). Proposed circuit ensures high speed compared to the conventional ROs using negative skewed scheme, in which each inverter delay is reduced by pre-maturely switching on/off the transistors. In addition, by controlling the load capacitance of each inverter through digital control bits, a programmable frequency of oscillation was attained. Proposed RO performance is compared with two conventional designs under same conditions. From simulation, it has been observed that the proposed circuit has shown a higher frequency of oscillations (283 KHz) compared to the conventional designs (76.52 KHz and 144.9 KHz) under same conditions. Due to the programmable feature, the circuit is able to generate 8 different linearly spaced frequencies ranging from 241.2 KHz to 283 KHz depending upon three digital control bits with almost rail-to-rail voltage swing. The circuit is a potential on-chip clock generator in many real-world flexible systems, such as, smart packaging, wearable devices, RFIDs and displays that need multi frequencies.