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Publicações

Publicações por João Paiva Cardoso

2017

Embedded Computing for High Performance: Efficient Mapping of Computations Using Customization, Code Transformations and Compilation

Autores
Cardoso, JMP; Coutinho, JGF; Diniz, PC;

Publicação
Embedded Computing for High Performance: Efficient Mapping of Computations Using Customization, Code Transformations and Compilation

Abstract
Embedded Computing for High Performance: Design Exploration and Customization Using High-level Compilation and Synthesis Tools provides a set of real-life example implementations that migrate traditional desktop systems to embedded systems. Working with popular hardware, including Xilinx and ARM, the book offers a comprehensive description of techniques for mapping computations expressed in programming languages such as C or MATLAB to high-performance embedded architectures consisting of multiple CPUs, GPUs, and reconfigurable hardware (FPGAs). The authors demonstrate a domain-specific language (LARA) that facilitates retargeting to multiple computing systems using the same source code. In this way, users can decouple original application code from transformed code and enhance productivity and program portability. After reading this book, engineers will understand the processes, methodologies, and best practices needed for the development of applications for high-performance embedded computing systems. Focuses on maximizing performance while managing energy consumption in embedded systems Explains how to retarget code for heterogeneous systems with GPUs and FPGAs Demonstrates a domain-specific language that facilitates migrating and retargeting existing applications to modern systems Includes downloadable slides, tools, and tutorials.

2017

Message from ANDARE'17 general and program chairs

Autores
Bartolini, A; Cardoso, JMP; Silvano, C; Palermo, G; Barbosa, J; Marongiu, A; Mustafa, D; Rohou, E; Mantovani, F; Agosta, G; Martinovic, J; Pingali, K; Slaninová, K; Benini, L; Cytowski, M; Palkovic, M; Gerndt, M; Sanna, N; Diniz, P; Rusitoru, R; Eigenmann, R; Patki, T; Fahringer, T; Rosendard, T;

Publicação
ACM International Conference Proceeding Series

Abstract

2021

An ensemble of autonomous auto-encoders for human activity recognition

Autores
Garcia, KD; de Sa, CR; Poel, M; Carvalho, T; Mendes Moreira, J; Cardoso, JMP; de Carvalho, ACPLF; Kok, JN;

Publicação
NEUROCOMPUTING

Abstract
Human Activity Recognition is focused on the use of sensing technology to classify human activities and to infer human behavior. While traditional machine learning approaches use hand-crafted features to train their models, recent advancements in neural networks allow for automatic feature extraction. Auto-encoders are a type of neural network that can learn complex representations of the data and are commonly used for anomaly detection. In this work we propose a novel multi-class algorithm which consists of an ensemble of auto-encoders where each auto-encoder is associated with a unique class. We compared the proposed approach with other state-of-the-art approaches in the context of human activity recognition. Experimental results show that ensembles of auto-encoders can be efficient, robust and competitive. Moreover, this modular classifier structure allows for more flexible models. For example, the extension of the number of classes, by the inclusion of new auto-encoders, without the necessity to retrain the whole model. (c) 2021 The Authors. Published by Elsevier B.V. This is an open access article under the CC BY license (http:// creativecommons.org/licenses/by/4.0/).

2018

Message from DASIP'2018 General and Program Chairs

Autores
Cardoso, JMP; Casseau, E; Langlois, P; Juárez, E;

Publicação
Conference on Design and Architectures for Signal and Image Processing, DASIP

Abstract

2018

Message from general and program co-chairs

Autores
Silvano, C; Cardoso, JMP; Fornaciari, W; Huebner, M;

Publicação
ACM International Conference Proceeding Series

Abstract

2019

Unfolding and folding: A new approach for code restructuring targeting HLS for FPGAs

Autores
Ferreira, AC; Cardoso, JMP;

Publicação
5th International Workshop on FPGAs for Software Programmers, FSP 2018, co-located with International Conference on Field Programmable Logic and Applications, FPL 2018

Abstract
FPGAs are becoming a popular solution for accelerating the execution of software applications. The use of high level synthesis (HLS) tools intends to provide levels of abstraction comfortable to software developers when targeting FPGA-based hardware accelerators. However, the need to restructure the software code and to use adequate directives require both mastering the HLS tool used and FPGA hardware. This paper presents our efforts to provide a new approach for code restructuring, intended to help software developers in achieving efficient hardware implementations. Our approach uses an unfolded graph representation, which is generated from program execution traces, together with graph-based optimizations such as folding to generate suitable C code to input to HLS tools, such as Vivado HLS. The experiments show that our approach is capable of generating C code that results in efficient hardware implementations only otherwise achievable using manual restructuring of the input software code and manual insertion of adequate directives. © VDE VERLAG GMBH · Berlin · Offenbach

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