Abstract
Data-mining over software can reveal similar patterns on software code. This can give important insights for the design of hardware cores, especially considering the benefits of the merge of software kernels and their implementation as a single hardware core. However, software codes have characteristics that make inadequate the direct use of typical data mining tools, mainly related to their large number of samples and the imprecise definition of code features for mining. Those characteristics affect negatively the performance of the most known data mining methods. To solve this problem, we propose in this paper the use of three techniques: the Normalized Compression Distance, the Neighbor Joining, and the Fast Newman algorithm. We combine these three techniques and propose a new approach for data mining of code repositories (DAMICORE). DAMICORE works with different types of code representations. Experiments reveal DAMICORE can indicate important software similarities at source code level. Specifically, merging soft-ware kernels identified by DAMICORE results in FPGA cores with size smaller than the overall hardware size needed when implementing a core for each kernel. © 2011 IEEE.

Abstract
In embedded reconfigurable computing systems, general purpose processors (GPPs) are typically extended with coprocessors to meet specific goals, such as higher performance and/or energy savings. Coprocessors can range from specialized modules which execute a specific task to reconfigurable arrays of ALUs. This paper presents our ongoing work on techniques to dynamically offload computations being executed by a GPP to a coprocessor. We present our method for identifying repetitive instruction traces, named as Mega blocks, as well as transformations which can be applied over those Mega blocks. We also present a proof-of-concept implementation of a system which transparently moves computations from a GPP to a Specialized Reconfigurable Array (SRA). Finally, we present our current and planned work. © 2011 IEEE.

Abstract
Context-aware mobile applications can benefit from context inference adaptation based on run-time operating conditions, such as battery life or sensor availability. Developing applications with such adaptable behavior, however, is notoriously cumbersome, as developers need to deal with low-level system interfacing and programming issues. In this paper we describe a domain-specific language (DSL) and a middleware infrastructure to support the specification, deployment and maintenance of run-time adaptable context inference processes. We illustrate the benefits of our approach via a case study, highlighting the new abstractions that facilitate the specification of adaptable behavior using different algorithms and the corresponding varying parameter settings, with a specific goal of minimizing the energy while maintaing acceptable end-application performance and accuracy. © 2011 IEEE.

Abstract
The common approach to include non-functional requirements in tool chains for hardware/software embedded systems requires developers to manually change the software code and/or the hardware, in an error-prone and tedious process. In the REFLECT research project we explore a novel approach where safety requirements are described using an aspect-and strategy-oriented programming language, named LARA, currently under development. The approach considers that the weavers in the tool chain use those safety requirements specified as aspects and strategies to produce final implementations according to specific design patterns. This paper presents our approach including LARA-based examples using an avionics application targeting the FPGA-based embedded systems consisting of a general purpose processor (GPP) coupled to custom computing units.

Abstract
The identification of patterns on large repositories of code can be of paramount importance to guide the design of new hardware accelerators, To acquire the suitability of a certain hardware accelerator and to generate application-specific architectures that maximize hardware reuse. This work intends to research and develop methods to both acquire the presence of a given pattern (map-suitability) and to identify common and highly similar patterns in code repositories (design-suggestions). The approach being proposed is based on a number of identification layers that refine the selections at each stage. We analyze two possible complementary options for a high-level layer. A first option is based on the representation of programs as a sequence of symbols and string matching and clustering algorithms are then used to expose similar patterns. A second option is based on tree matching techniques for identifying the presence of user's input patterns in the programs under inspection. We are evaluating our approach using the MiBench, Media-Bench, UTDSP, and SNU code repositories. The results show the potential of our approach to identify approximate patterns that can be implemented by merging highly similar structures. © 2010 IEEE.

Abstract
Typical computing systems based on general purpose processors (GPPs) are extended with coarse-grained reconfigurable arrays (CGRAs) to provide higher performance and/or energy savings. In order for applications to take advantage of these computing systems, efficient dynamic mapping techniques are required. Those dynamic mapping techniques will be responsible for automatically moving computations originally running in the GPP to the CGRA. The concept of dynamic compilation, widespread in the context of JIT compilation to GPPs, is receiving more attention by the reconfigurable computing community. This paper presents our approach to dynamically map computations to CGRAs coupled to a GPP. Specifically, we present the identification of large sequences of instructions, MegaBlocks, being executed in a GPP. These MegaBlocks are then mapped to the target CGRA. We evaluate the potential of the MegaBlocks over Basic Blocks and SuperBlocks to increase the IPC when targeting a CGRA and considering the execution of a number of representative benchmarks. © 2010 IEEE.