Abstract
This chapter describes the design-flow approach developed in the REFLECT project as presented originally in [1]. Over the course of the project, this design-flow has evolved and has been extended into a fully operational toolchain. We begin by presenting an overview of the underlying aspect-oriented compilation flow followed by an extended description of the design-flow and its toolchain. © Springer Science+Business Media New York 2013. All rights are reserved.

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Abstract
Today, in our landscape perception exists a gap that needs to be fulfilled. It's important to increase the coverage, temporal and spatial resolution in order to cover this gap, as well as reduce costs with human resources that usually take this kind of tasks. Unmanned Autonomous vehicles with their inherent autonomy and reduced needs of human and communication resources, can provide additional capabilities and a new innovative solution to this problem This paper presents and describes the participation of ICARUS Team at euRathlon 2015 and the importance of this type of events performed with multiple unnamed systems.

Abstract

Abstract
The paper presents the approach followed at the Faculty of Engineering of the University of Porto, to introduce design automation tools and structured design techniques in the first course on digital system design of our Integrated Master in Electrical and Computer Engineering. Digital Systems Laboratory is an introductory course on digital design, with the classical task of teaching Boolean algebra and combinational and sequential circuit design, using gates, flip-flops and medium complexity components/function blocks like counters and shift-registers. The need to cope with new curriculum requirements and modern digital design demands, motivated an extensive reformulation of the course contents and organization, leading to the introduction of the use of hardware description languages and synthesis tools, in order to implement small systems, of increasingly complex nature, on an FPGA platform. At the same time its coverage was extended to include low-level processor architecture issues, and to teach assembly programming for the MIPS processor. The paper describes how this reformulation was carried out. It presents the course contents and timeline, and discusses the main choices that were made. The paper also describes the laboratory experiments that were developed and discusses some of the challenges and results obtained so far. © 2014 IEEE.

Abstract
The genetic algorithm is a general purpose optimization metaheuristic for solving complex optimization problems. Because the algorithm usually requires a large number of iterations to evolve a population of solutions to good final solutions, it normally exhibits long execution times, especially if running on low-performance conventional processors. In this work, we present a scalable computing array to parallelize and accelerate the execution of cellular GAs (cGAs). This is a variant of genetic algorithms which can conveniently exploit the coarse-grain parallelism afforded by custom parallel processing. The proposed architecture targets Xilinx FPGAs and was implemented as an auxiliary processor of an embedded soft-core CPU (MicroBlaze). To facilitate the customization for different optimization problems, a high-level synthesis design flow is proposed where the problem-dependent operations are specified in C++ and synthesised to custom hardware, thus demanding of the programmer only minimal knowledge of low-level digital design for FPGAs. To demonstrate the efficiency of the array processor architecture and the effectiveness of the design methodology, the development of a hardware solver for the minimum energy broadcast problem in wireless ad hoc networks is employed as a use case. Implementation results for a Virtex-6 FPGA show significant speedups, especially when comparing to embedded processors used in current FPGA devices.