Abstract
This article addresses the 3-D localization of a stand-alone acoustic beacon based on the Principle of Synthetic Baseline using a single receiver on board a surface vehicle. The process only uses the passive reception of an acoustic signal with no explicit synchronization, interaction, or communication with the acoustic beacon. The localization process exploits the transmission of periodic signals without synchronization to a known time reference to estimate the time-of-arrival (ToA) with respect to an absolute time basis provided by the global navigation satellite system (GNSS). We present the development of the acoustic signal acquisition system, the signal processing algorithms, the data processing of times-of-arrival, and an estimator that uses times-of-arrival and the coordinates where they have been collected to obtain the 3-D position of the acoustic beacon. The proposed approach was validated in a real field application on a search for an underwater glider lost in September 2021 near the Portuguese coast.

Abstract
Accurate localization is a critical task in underwater navigation. Typical localization methods use a set of acoustic sensors and beacons to estimate relative position, whose geometric configuration has a significant impact on the localization accuracy. Although there is much effort in the literature to define optimal 2D or 3D sensor placement, the optimal sensor placement in irregular and constrained 3D surfaces, such as autonomous underwater vehicles (AUVs) or other structures, is not exploited for improving localization. Additionally, most applications using AUVs employ commercial acoustic modems or compact arrays, therefore the optimization of the placement of spatially independent sensors is not a considered issue. This article tackles acoustic sensor placement optimization in irregular and constrained 3D surfaces, for inverted ultra-short baseline (USBL) approaches, to improve localization accuracy. The implemented multi-objective memetic algorithm combines an evaluation of the geometric sensor's configuration, using the Cramer-Rao Lower Bound (CRLB), with the incidence angle of the received signal. A case study is presented over a simulated homing and docking scenario to demonstrate the proposed optimization algorithm.

Abstract

Abstract
The development of applications for high-performance Field Programmable Gate Array (FPGA) based embedded systems is a long and error-prone process. Typically, developers need to be deeply involved in all the stages of the translation and optimization of an application described in a high-level programming language to a lower-level design description to ensure the solution meets the required functionality and performance. This paper describes the use of a novel aspect-oriented hardware/software design approach for FPGA-based embedded platforms. The design-flow uses LARA, a domain-specific aspect-oriented programming language designed to capture high-level specifications of compilation and mapping strategies, including sequences of data/computation transformations and optimizations. With LARA, developers are able to guide a design-flow to partition and map an application between hardware and software components. We illustrate the use of LARA on two complex real-life applications using high-level compilation and synthesis strategies for achieving complete hardware/software implementations with speedups of 2.5x and 6.8x over software-only implementations. By allowing developers to maintain a single application source code, this approach promotes developer productivity as well as code and performance portability.

Abstract
The Erlang programming language is a concurrency oriented functional language, based on the notion of independent processes and uses message passing for communication between processes. It is specially adapted to the realization of highly reliable distributed systems. In this paper it is analyzed the use of the Erlang's computational paradigm for the design and implementation of application specific heterogeneous computational systems. The main objective is to use for the low level implementation the same computational model used in high level view of the system. This will allow an easier and faster design space exploration and optimization. © 2010 IEEE.

Abstract
Cellular Genetic Algorithms (cGAs) exhibit a natural parallelism that makes them interesting candidates for hardware implementation, as several processing elements can operate simultaneously on subpopulations shared among them. This paper presents a scalable architecture for a cGA, suitable for FPGA implementation. A regular array of custom designed processing elements (PEs) works on a population of solutions that is spread into dual-port memory blocks locally shared by adjacent PEs. A travelling salesman problem with 150 cities was used to verify the implementation of the proposed cGA on a Virtex-6 FPGA, using a population of 128 solutions with different levels of parallelism (1, 4, 16 and 64 PEs). Results have shown that an increase of the number of PEs does not degrade the quality of the convergence of the iterative process, and that the throughput increases almost linearly with the number of PEs. Comparing with a software implementation running in a PC, the cGA with 64 PEs has shown a 45x speedup.