Abstract
This paper presents the computing infrastructure used in an autonomous unmanned small-scale sailboat. The system is based on a FPGA and includes custom designed interfaces for the various sensors and actuators used in the sailboat. The central processing unit is a 32-bit 50 MHz RISC microprocessor implemented as a soft IP core in the FPGA. The computing system runs uClinux, a simplified version of the popular Linux operating system. The usage of a reconfigurable platform enables a quick reconfiguration of the logic circuit implemented in the FPGA, facilitating the development stage and allowing a dynamic switch among different implementations, according to the navigation requirements and environmental conditions.

Abstract
This paper presents a custom processor designed to execute a time consuming function in a CFD application. The selected function implements the method TDMA (Tri-Diagonal Matrix Algorithm) for solving a tri-diagonal system of equations. The custom processor was implemented in a commercial PCI prototyping board based on Virtex4LX FPGAs and uses a dedicated memory cache system, address generators and a deep pipelined floating-point datapath. Running at 100MHz and assuming the input data already in the cache memories, the system reaches a throughput greater than 1.4GFLOPS.

Abstract
This paper presents an embedded hardware/software implementation for the computing system of a small scale unmanned autonomous sailing boat. The system is integrated in a single XILINX FPGA, and hosts a Microblaze soft processor surrounded with heterogeneous, custom designed, control and processing modules than handle the interface with all the sensors, actuators and communication devices of the sailing boat. These interfacing modules implement tasks that have been decentralized from the main processor, thus alleviating its computational load and providing processing time for higher level software applications. Using an FPGA to implement an integrated single-chip computing system, as an alternative to conventional processors, has proven to be a very flexible solution as it eases the migration of computation tasks between the hardware and software domains, and more importantly, allowing the rapid adaptation of the digital interfacing hardware in order to support additional peripheral devices required for an application mission. The software component of the boat's control system runs on the top of the uClinux embedded operating system and is formed by various concurrent applications developed in C with the standard Linux libraries. The remote monitoring, configuration and operation of the sailing boat is done via a WiFi link, using a graphics interactive application that runs on a conventional PC.

Abstract
This paper addresses the design and implementation of feedback controllers for the direction of autonomous robotic sailboats. In order to design such a controller, it is important to determine a model for the sailboat dynamics during turns. However, there are many uncontrollable factors that may affect the direction of the sailboat, which make it difficult to obtain an accurate model and require a lot of sensors to feed a proper controller. Instead, we assume a rather simple model relating the most important variables and concentrate on data that can easily be available with simple low-cost sensors, compensating the lack of accuracy of the model with the robustness of the controller. We describe our approach to extract the parameters of such a dynamic model using data obtained in field experiments and we show how to use this model to tune a PI controller. As a case study, we use the FASt vehicle, a 2.5 m long robotic sailing boat capable of fully autonomous navigation through a set of predefined marks. Experimental results show the performance of the designed controller. © 2010 IEEE.

Abstract

Abstract
This paper describes a micro-architecture for a custom programmable FPGA-based processor, with direct support for streaming and vector computations relying on custom cache memory storage. The processor combines a custom data-path with several parallel data ports for accessing operands in streaming mode thus efficiently supporting nested looping constructs found in high-level languages while mitigating the impact on external memory bandwidth. The architecture leverages the strided access patterns of streaming data access using a microcoded sequencer with multi-dimensional nested looping capability. We present synthesis results for the main components of the architecture on a Xilinx's Virtex-4 FPGA device. The results reveal the architecture to be extremely flexible and consume few FPGA resources. © 2011 IEEE.