Abstract
The growing processing capabilities of mobile devices coupled with portable and wearable sensors have enabled the development of context-aware services tailored to the user environment and its daily activities. The problem of determining the user context at each particular point in time is one of the main challenges in this area. In this paper, we describe the approach pursued in the UPCASE project, which makes use of sensors available in the mobile device as well as sensors externally connected via Bluetooth. We describe the system architecture from raw data acquisition to feature extraction and context inference. As a proof of concept, the inference of contexts is based on a decision tree to learn and identify contexts automatically and dynamically at runtime. Preliminary results suggest that this is a promising approach for context inference in several application scenarios.

Abstract
Loop unrolling plays an important role in compilation for Reconfigurable Processing Units (RPUs) as it exposes operator parallelism and enables other transformations (e.g., scalar replacement). Deciding when and where to apply loop unrolling, either fully or partially, leads to large design space exploration problems. In order to cope with these vast spaces, researchers have explored the application of design estimation techniques. Using estimation, tools can conduct early evaluation of the impact and interplay of transformations in both the required resources and expected performance. In this paper we present some of the current approaches and issues related to estimation of the loop unrolling impact when targeting RPUs.

Abstract
The development of applications for high-performance embedded systems is typically a long and error-prone process. In addition to the required functions, developers must consider various and often conflicting non-functional application requirements such as performance and energy efficiency. The complexity of this process is exacerbated by the multitude of target architectures and the associated retargetable mapping tools. This paper introduces an Aspect-Oriented Programming (AOP) approach that conveys domain knowledge and non-functional requirements to optimizers and mapping tools. We describe a novel AOP language, LARA, which allows the specification of compilation strategies to enable efficient generation of software code and hardware cores for alternative target architectures. We illustrate the use of LARA for code instrumentation and analysis, and for guiding the application of compiler and hardware synthesis optimizations. An important LARA feature is its capability to deal with different join points, action models, and attributes, and to generate an aspect intermediate representation. We present examples of our aspect-oriented hardware/software design flow for mapping real-life application codes to embedded platforms based on Field Programmable Gate Array (FPGA) technology. © 2012 ACM.

Abstract
The development of applications for high-performance Field Programmable Gate Array (FPGA) based embedded systems is a long and error-prone process. Typically, developers need to be deeply involved in all the stages of the translation and optimization of an application described in a high-level programming language to a lower-level design description to ensure the solution meets the required functionality and performance. This paper describes the use of a novel aspect-oriented hardware/software design approach for FPGA-based embedded platforms. The design-flow uses LARA, a domain-specific aspect-oriented programming language designed to capture high-level specifications of compilation and mapping strategies, including sequences of data/computation transformations and optimizations. With LARA, developers are able to guide a design-flow to partition and map an application between hardware and software components. We illustrate the use of LARA on two complex real-life applications using high-level compilation and synthesis strategies for achieving complete hardware/software implementations with speedups of 2.5x and 6.8x over software-only implementations. By allowing developers to maintain a single application source code, this approach promotes developer productivity as well as code and performance portability.

Abstract
This paper describes a micro-architecture for a custom programmable FPGA-based processor, with direct support for streaming and vector computations relying on custom cache memory storage. The processor combines a custom data-path with several parallel data ports for accessing operands in streaming mode thus efficiently supporting nested looping constructs found in high-level languages while mitigating the impact on external memory bandwidth. The architecture leverages the strided access patterns of streaming data access using a microcoded sequencer with multi-dimensional nested looping capability. We present synthesis results for the main components of the architecture on a Xilinx's Virtex-4 FPGA device. The results reveal the architecture to be extremely flexible and consume few FPGA resources. © 2011 IEEE.

Abstract
High-performance computing applications that will run on future exascale-class supercomputing systems are projected to encounter accelerated rates of faults and errors. For these large-scale systems, maintaining fault resilient operation is a key challenge. The most widely used resiliency approach today, which is based on checkpoint and rollback (C/R) recovery, is not expected to remain viable in the presence of frequent errors and failures. In this paper, we present a framework for enabling application-level recovery from error states through fault amelioration. Our approach is based on programming model extensions that enable algorithm-based fault amelioration knowledge to be expressed as an intrinsic feature of the programming environment. This is accomplished through a set of language extensions that are supported by a compiler infrastructure and a runtime system. We experimentally demonstrate that the framework enables recovery from errors in the program state with low overhead to the application performance. © 2015 IEEE.