Abstract
Decision trees are often preferred when implementing Machine Learning in embedded systems for their simplicity and scalability. Hoeffding Trees are a type of Decision Trees that take advantage of the Hoeffding Bound to allow them to learn patterns in data without having to continuously store the data samples for future reprocessing. This makes them especially suitable for deployment on embedded devices. In this work we highlight the features of a HLS implementation of the Hoeffding Tree. The implementation parameters include the feature size of the samples (D), the number of output classes (K), and the maximum number of nodes to which the tree is allowed to grow (Nd). We target a Xilinx MPSoC ZCU102, and evaluate: the design's resource requirements and clock frequency for different numbers of classes and feature size, the execution time on several synthetic datasets of varying sizes (N) and the execution time and accuracy for two datasets from UCI. For a problem size of D=3, K=5, and N=40000, a single decision tree operating at 103MHz is capable of 8.3x faster inference than the 1.2 GHz ARM Cortex-A53 core. Compared to a reference implementation of the Hoeffding tree, we achieve comparable classification accuracy for the UCI datasets.

Abstract
This paper investigates the use of mixed-signal test support ICs to extend a digital, board level test infrastructure to the analog section of a mixed-signal board. The architecture of a prototype test support IC is described and its application to the test of an infrared emitter-receiver board is discussed.

Abstract
Mixed hardware/software applications may profit from the use of dynamically reconfigurable hardware for improved performance and adaptability. For this class of systems, the hardware, like the software, can be adapted during execution to the data being processed or to the reactions of the external system being controlled. This paper presents the prototype of an interactive system that supports the rapid development of such applications for a personal computer. The LISP-based prototype supports the assembly of hardware configurations in runtime by combination of component blocks from libraries; it also provides tools for partitioning computations described by a domain-independent data-flow model between software and hardware implementations. Whatever the implementation mode, computations are invoked in a uniform manner, making the dynamically reconfigurable hardware transparent to the user.

Abstract
This paper presents an offline tool-chain which automatically extracts loops (Mega blocks) from Micro Blaze instruction traces and creates a tailored Reconfigurable Processing Unit (RPU) for those loops. The system moves loops from the CPU to the RPU transparently, at runtime, and without changing the executable binaries. The system was implemented in an FPGA and for the tested kernels measured speedups ranged between 3.9x and 18.2x for a Micro Blaze CPU without cache. We estimate speedups from 1.03x to 2.01x, when comparing to the best estimated performance achieved with a single Micro Blaze. © 2011 IEEE.

Abstract
This paper presents a routing protocol for wireless sensor networks (WSN), established on the basis of fundamental concepts in source based routing (SBR) for ad hoc networks and minimum cost forwarding (MCF) methods for heterogeneous WSNs. Neither routing tables nor network topology information is maintained at sensor level, which makes the proposed protocol part of the reactive routing protocols class. Despite the lack of network information at the sensor, the packets from the sink node to sensors, and viceversa, always follow the optimal communication path with minimum cost. Simulation results have shown that the proposed protocol performs better than MCF protocol alone, and nodes always route the packets through the optimal path up to destination. In fact, according to the energy consumption and throughput found by simulation, this protocol improves on the MCF protocol for applications where the sink node, acting as a server or base station (BS), generates significant amounts of network traffic. All results are based on simulations and data treatment performed with OMNet++ 4, Matlab 7 and Microsoft Visual Studio2010(C#) platform tools.

Abstract
Meeting safety requirements typically require substantial invasive extensions to applications. Even in the absence of faults, the overhead associated with these invasive extensions may unacceptably increase execution time. In this paper we focus on a number of experiments with schemes for error detection, having a 3D Path Planning application for an avionics system as case study. We analyze how these error detection schemes can be implemented to meeting system's time budget. The experiments allowed us to acquire the requirements for automating the application of the error detection schemes in the context of a hardware/software design-flow, and to determine how those schemes can be addressed using a novel approach where safety requirements are described using an aspect- and strategy-oriented programming language, named LARA. For our experiments and validation, we consider an FPGA-based embedded system consisting of a general purpose processor (GPP) coupled to custom computing units which are primarily used for hardware acceleration and for implementing fault detection schemes. © 2012 IEEE.