Abstract
This paper presents a novel approach to accelerate program execution by mapping repetitive traces of executed instructions, called Megablocks, to a runtime reconfigurable array of functional units. An offline tool suite extracts Megablocks from microprocessor instruction traces and generates a Reconfigurable Processing Unit (RPU) tailored for the execution of those Megablocks. The system is able to transparently movebcomputations from the microprocessor to the RPU at runtime. A prototype implementation of the system using a cacheless MicroBlaze microprocessor running code located in external memory reaches speedups from 2.2x to 18.2x for a set of 14 benchmark kernels. For a system setup which maximizes microprocessor performance by having the application code located in internal block RAMs, speedups from 1.4x to 2.8x were estimated.

Abstract
Human motion capture systems are used by medical staff for detecting and identifying mobility impairments, early stages of certain pathologies and can also be used for evaluation of the effectiveness of surgical or rehabilitation intervention. Other applications may involve athlete's performance, occupational safety, among others. Presently there is a considerable number of solutions available, however these systems present some drawbacks, as they are often expensive, considerably complex, difficult to wear and use in a daily basis, and very uncomfortable for the patient. With the purpose of solving the above mentioned problems, a new wearable locomotion data capture system for gait analysis is under development. This system will allow the measurement of several locomotion-related parameters in a practical and non-invasive way, comfortable to the user, which will also be reusable that can be used by patients from light to severe impairments or disabilities. The present paper gives an overview of the research that is being developed, regarding the design of the wearable equipment, textile support, and communications.

Abstract
In this paper a new wearable locomotion data capture system for gait analysis is presented. The system under development intends to help clinicians to detect and identify mobility impairments as well as to evaluate the effectiveness of surgical or rehabilitation intervention. The proposed system allows the measurement of kinematic and biomechanical parameters in a practical and comfortable weft knitted legging, in which the sensors are incorporated.

Abstract
Digital circuits exposed to environments with high levels of radiation, such as those found in High Energy Physics experiments, are prone to Single Event Upsets. These upsets impact the reliability of the circuit. In order to mitigate the effects of the upsets, several well-known techniques for use with register transfer level (RTL) circuit descriptions have been proposed over the years. They typically have a large impact on circuit size and power consumption. Therefore, they are often applied only to the more critical modules of the system. Additionally, the manual implementation of those techniques has a significant cost in terms of time and design effort, involving both RTL changes and tailoring of the synthesis flow to avoid optimizing away the additional hardware. This paper describes an automated workflow that reduces the time for implementing SEU mitigation techniques, avoids the errors caused by manual alteration of the RTL descriptions, and enables the designer to explore different alternatives quickly. The paper describes the application of the workflow to three digital circuits and discusses the data obtained from the implementation of the different mitigation techniques.

Abstract
This chapter describes the design-flow approach developed in the REFLECT project as presented originally in [1]. Over the course of the project, this design-flow has evolved and has been extended into a fully operational toolchain. We begin by presenting an overview of the underlying aspect-oriented compilation flow followed by an extended description of the design-flow and its toolchain. © Springer Science+Business Media New York 2013. All rights are reserved.

Abstract
This paper presents a binary acceleration approach based on extending a General Purpose Processor (GPP) with a Reconfigurable Processing Unit (RPU), both sharing an external data memory. In this approach repeating sequences of GPP instructions are migrated to the RPU. The RPU resources are selected and organized off-line using execution trace information. The RPU core is composed of Functional Units (FUs) that correspond to single CPU instructions. The FUs are arranged in stages of mutually independent operations. The RPU can enable several stages in tandem, depending on the data dependencies. External data memory accesses are handled by a configurable dual-port cache. A prototype implementation of the architecture on a Spartan-6 FPGA was validated with 12 benchmarks and achieved an overall geometric mean speedup of 1.91x.