Abstract

Abstract
Our work proposes a hardware architecture for a Long Short-Term Memory (LSTM) Neural Network, aiming to outperform software implementations, by exploiting its inherent parallelism. The main design decisions are presented, along with the proposed network architecture. A description of the main building blocks of the network is also presented. The network is synthesized for various sizes and platforms, and the performance results are presented and analyzed. Our synthesized network achieves a 251 times speed-up over a custom-built software network, running on an i7-3770k Desktop computer, proving the benefits of parallel computation for this kind of network.

Abstract
Filter-bank Multicarrier (FBMC) modulation has been proposed as a 5G waveform candidate due to its better spectral efficiency and lower out-of-band emissions compared to OFDM. This paper presents an FPGA-based implementation of a Frequency Spreading FBMC-OQAM baseband modulator and evaluates it in terms of performance, resource utilization and power consumption. The proposed system is then compared with published Polyphase Network (PPN) FBMC-OQAM designs, focusing on resource utilization. The results suggest that the higher computational complexity of FS-FBMC systems does not directly result in higher resource utilization, which makes FS-FBMC a convenient scheme for implementing FBMC designs on FPGA.

Abstract
The usage of application-specific hardware based on Field-Programmable Gate Arrays (FPGA) has proven its benefits. Current system-on-chips, which contain FPGA fabric, supporting dynamic partial reconfiguration, enable a dynamic hardware acceleration for hardware/software co-designs. With the trend to consolidate multiple computing systems into a single system, applications with mixed criticalities can come into conflict. With our approach, we are exploring the possibility to utilize dedicated hardware for the system management and benefit from possible parallelization of applications and system management tasks.

Abstract
5G heterogeneity will cover a huge diversity of use cases, ranging from enhanced-broadband to low-throughput and low-power communications. To address such requirements variety, this paper proposes a parallel-pipelined architecture for an OFDM baseband modulator with clock frequency run-time adaptation through dynamic frequency scaling (DFS). It supports a set of OFDM numerologies recently proposed for 5G communication systems. The parallel-pipelined architecture can achieve high throughputs at low clock frequencies (up to 520.3 MSamples/s at 160 MHz) and DFS allows for the adjustment of baseband processing clock frequency according to immediate throughput demands. The application of DFS increases the system’s power efficiency by allowing power savings up to 62.5%; the resource and latency overhead is negligible. © Springer International Publishing AG, part of Springer Nature 2018.

Abstract
Filter-bank Multicarrier Modulation (FBMC) is a 5G waveform candidate with improved spectral efficiency and out-of-band emissions performance compared to OFDM. To address the challenge of designing flexible hardware infrastructures for future wireless communications, this paper presents a dynamically reconfigurable FPGA-based Frequency Spreading FBMC (FS-FBMC) baseband modulator. Based on a detailed modulator datapath analysis, the proposed architecture combines static multi-mode modules with dynamic partial reconfiguration (DPR) to achieve a flexible and evolvable system. Results show that our design is resource-efficient, due to hardware virtualization. Moreover, low-latency reconfiguration of static multimode modules combined with ICAP overclocking results in submillisecond reconfiguration times which are viable in the context of flexible communication systems, such as Cognitive Radios.