Abstract
This chapter presents a one-way method for synchronization at the media access control (MAC) layer of nodes and a circuit based on that in a wearable sensor network. The proposed approach minimizes the time skew with an accuracy of half of clock cycle in average. The work is intended to be used in a router integrated circuit (IC) designed for wearable systems. In particular, we address the need for good time synchronization in the simultaneous acquisition of surface electromyographic signals of several muscles. In our main application case, the electrodes are embedded in patient clothes connected to sensor nodes (SNs) equipped with analog-to-digital converters. The SNs are connected together in a network using conducting yarns embedded in the clothes. In the context of such wearable sensor networks, the main contributions of this work are the evaluation of existing protocols for synchronization, the description of a simpler, resource-efficient synchronization protocol, and its analysis, including the determination of the average local and global clock skew and of the synchronization probability in the presence of link failures. Both theoretical analysis and experimental results, in wired wearable networks, show that the proposed protocol has a better performance than precision time protocol (PTP), a standard timing protocol for both single and multihop situations. The proposed approach is simpler, requires no calculations, and exchanges fewer messages. Experimental results obtained with an implementation of the protocol in 0.35 µm complementary metal oxide semiconductor (CMOS) technology show that this approach keeps the one-hop average clock skew around 4.6 ns and peak-to-peak skew around 50 ns for a system clock frequency of 20 MHz. © The Institution of Engineering and Technology 2017.

Abstract
This chapter addresses a wearable body area network (BAN) system for both medical and nonmedical applications, especially those including a large number of sensors at BAN scale (<250), embedded in textile and with high data rate (<9+9 MHz) communication demands. The overall system includes an on-body central processing module (CPM) connected to a computer via a wireless link and a wearable sensor network. Due to the fixed location of the sensors and the possibility of using conductive yarns in textiles, a wired network has been considered for the wearable components. Employing conductive yarns instead of using wireless links provides a more reliable communication, higher data rates and throughput, and less power consumption. The wearable unit is composed of two types of circuits, the sensor nodes (SNs) and a base station (BS), all connected to each other with conductive yarns forming a mesh topology with the base node at the center. The reliability analysis shows that communication in a multi-hop connection of sensors in mesh topology is more reliable than in the conventional star topology. From the standpoint of the network, each SN is a four port router capable of handling packets from destination nodes to the BS. The end-to-end communication uses packet switching for packet delivery from SNs to the BS or in the reverse direction, or between SNs. The communication module has been implemented in a low power field programmable gate arrays (FPGA) and a microcontroller. The maximum data rate of the system is 9+9 Mbps while supporting tens of sensors, which is much more than current BAN applications need. The suitability of the proposed system for utilization in real applications has been demonstrated experimentally. © The Institution of Engineering and Technology 2017.

Abstract
Sequential Minimal Optimization (SMO) is the traditional training algorithm for Support Vector Machines (SVMs). However, SMO does not scale well with the size of the training set. For that reason, Stochastic Gradient Descent (SGD) algorithms, which have better scalability, are a better option for massive data mining applications. Furthermore, even with the use of SGD, training times can become extremely large depending on the data set. For this reason, accelerators such as Field-programmable Gate Arrays (FPGAs) are used. This work describes an implementation in hardware, using FPGA, of a fully parallel SVM using Stochastic Gradient Descent. The proposed FPGA implementation of an SVM with SGD presents speedups of more than 10,000x relative to software implementations running on a quad-core processor and up to 319x compared to state-of-the-art FPGA implementations while requiring fewer hardware resources. The results show that the proposed architecture is a viable solution for highly demanding problems such as those present in big data analysis.

Abstract

Abstract
In future wireless communication systems, several radio access technologies will coexist and interwork to provide a great variety of services with different requirements. Thus, the design of flexible and reconfigurable hardware is a relevant topic in wireless communications. The combination of high performance, programmability and flexibility makes Field-programmable gate array a convenient platform to design such systems, especially for base stations. This paper describes a dynamically reconfigurable baseband modulator for Orthogonal Frequency Division Multiplexing and Filter-bank Multicarrier modulation waveforms implemented on a Virtex-7 board. The design features Dynamic Partial Reconfiguration (DPR) capabilities to adapt its mode of operation at run-time and is compared with a functionally equivalent static multi-mode design regarding processing throughput, resource utilization, functional density and power consumption. The DPR-based design implementation reserves about half the resources used by static multi-mode counterpart. Consequently, the baseband processing dynamic power consumption observed in the DPR-based design is between 26 mW to 90 mW lower than in the static multi-mode design, representing a dynamic power reduction between 13% to 52%. The worst-case DPR latency measured was 1.051 ms, while the DPR energy overhead is below 1.5 mJ. Considering latency requirements for modern wireless standards and power consumption constraints for commercial base stations, the DPR application is shown to be valuable in multi-standard and multi-mode systems, as well as in scenarios such as multiple-input and multiple-output or dynamic spectrum aggregation.

Abstract
The K-means algorithm is widely used to find correlations between data in different application domains. However, given the massive amount of data stored, known as Big Data, the need for high-speed processing to analyze data has become even more critical, especially for real-time applications. A solution that has been adopted to increase the processing speed is the use of parallel implementations on FPGA, which has proved to be more efficient than sequential systems. Hence, this paper proposes a fully parallel implementation of the K-means algorithm on FPGA to optimize the system & x2019;s processing time, thus enabling real-time applications. This proposal, unlike most implementations proposed in the literature, even parallel ones, do not have sequential steps, a limiting factor of processing speed. Results related to processing time (or throughput) and FPGA area occupancy (or hardware resources) were analyzed for different parameters, reaching performances higher than 53 millions of data points processed per second. Comparisons to the state of the art are also presented, showing speedups of more than over a partially serial implementation.