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Publicações

Publicações por Luis Miguel Pinho

2013

Revisiting transactions in Ada

Autores
Barros, A; Pinho, LM;

Publicação
ACM SIGAda Ada Letters

Abstract
Classical lock-based concurrency control does not scale with current and foreseen multi-core architectures, opening space for alternative concurrency control mechanisms. The concept of transactions executing concurrently in isolation with an underlying mechanism maintaining a consistent system state was already explored in fault-tolerant and distributed systems, and is currently being explored by transactional memory, this time being used to manage concurrent memory access. In this paper we discuss the use of Software Transactional Memory (STM), and how Ada can provide support for it. Furthermore, we draft a general programming interface to transactional memory, supporting future implementations of STM oriented to real-time systems.

2016

Response time analysis of hard real-time tasks sharing software transactional memory data under fully partitioned scheduling

Autores
Barros, A; Yomsi, PM; Pinho, LM;

Publicação
2016 11TH IEEE INTERNATIONAL SYMPOSIUM ON INDUSTRIAL EMBEDDED SYSTEMS (SIES)

Abstract
Software transactional memory (STM) is a synchronisation paradigm which improves the parallelism and composability of modern applications executing on a multi-core architecture. However, to abort and retry a transaction multiple times may have a negative impact on the temporal characteristics of a real-time task set. This paper addresses this issue: It provides a framework in which an upper-bound on the worst-case response time of each task is derived, assuming that tasks are scheduled by following either the Non-Preemptive During Attempt (NPDA), Non-Preemptive Until Commit (NPUC) or Stack Resource Policy for Transactional Memory (SRPTM) policy.

2015

Non-preemptive and SRP-based fully-preemptive scheduling of real-time Software Transactional Memory

Autores
Barros, A; Pinho, LM; Yomsi, PM;

Publicação
JOURNAL OF SYSTEMS ARCHITECTURE

Abstract
Recent embedded processor architectures containing multiple heterogeneous cores and non-coherent caches renewed attention to the use of Software Transactional Memory (STM) as a building block for developing parallel applications. STM promises to ease concurrent and parallel software development, but relies on the possibility of abort conflicting transactions to maintain data consistency, which in turns affects the execution time of tasks carrying transactions. Because of this fact the timing behaviour of the task set may not be predictable, thus it is crucial to limit the execution time overheads resulting from aborts. In this paper we formalise a FIFO-based algorithm to order the sequence of commits of concurrent transactions. Then, we propose and evaluate two non-preemptive and one SRP-based fully-preemptive scheduling strategies, in order to avoid transaction starvation.

2015

Generalized Extraction of Real-Time Parameters for Homogeneous Synchronous Dataflow Graphs

Autores
Ali, HI; Akesson, B; Pinho, LM;

Publicação
2015 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing

Abstract

2015

Poster Abstract: Real-Time Support in the Proposal for Fine-Grained Parallelism in Ada

Autores
Pinho, LM; Moore, B; Michell, S; Taft, ST;

Publicação
2015 IEEE 36TH REAL-TIME SYSTEMS SYMPOSIUM (RTSS 2015)

Abstract

2015

A Formal Perspective on IEC 61499 Execution Control Chart Semantics

Autores
Lindgren, P; Lindner, M; Pereira, D; Pinho, LM;

Publicação
2015 IEEE TRUSTCOM/BIGDATASE/ISPA, VOL 3

Abstract
The IEC 61499 standard proposes an event driven execution model for distributed control applications for which an informal execution semantics is provided. Consequently, run-time implementations are not rigorously described and therefore their behavior relies on the interpretation made by the tool provider. In this paper, as a step towards a formal semantics, we focus on the Execution Control Chart semantics, which is fundamental to the dynamic behavior of Basic Function Block elements. In particular we develop a well-formedness criterion that ensures a finite number of Execution Control Chart transitions for each triggering event. We also describe the first step towards the mechanization of the well-formedness checking algorithm in the Coq proof-assistant so that, ultimately, we are able to show, once and for all, that this algorithm is effectively correct with respect to our proposed execution semantics. The algorithm is extractable from the mechanization in a correct-by-construction way, and can be directly incorporated in certified toolchain for analysis, compilation and execution of IEC 61499 models. As a proof of concept a prototype tool RTFM-4FUN has been developed. It performs well-formedness checks on Basic Function Blocks using the extracted algorithm's code.

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