2017
Autores
Nikolic, B; Pinho, LM;
Publicação
REAL-TIME SYSTEMS
Abstract
The Network-on-Chip (NoC) architecture is an interconnect network with a good performance and scalability potential. Thus, it comes as no surprise that NoCs are among the most popular interconnect mediums in nowadays available many-core platforms. Over the years, the real-time community has been attempting to make NoCs amenable to the real-time analysis. One such approach advocates to employ virtual channels. Virtual channels are hardware resources that can be used as an infrastructure to facilitate flit-level preemptions between communication traffic flows. This gives the possibility to implement priority-preemptive arbitration policies in routers, which is a promising step towards deriving real-time guarantees for NoC traffic. So far, various aspects of priority-preemptive NoCs were studied, such as arbitration, priority assignment, routing, and workload mapping. Due to a potentially large solution space, the majority of available techniques are heuristic-centric, that is, either pure heuristics, or heuristic-based search strategies are used. Such approaches may lead to an inefficient use of hardware resources, and may cause a resource over-provisioning as well as unnecessarily high design-cost expenses. Motivated by this reality, we take a different approach, and propose an integer linear program to solve the problems of priority assignment and routing of NoC traffic. The proposed method finds optimal routes and priorities, but also allows to reduce the search space (and the computation time) by fixing either priorities or routes, and derive optimal values for remaining parameters. This framework is used to experimentally evaluate both the scalability of the proposed method, as well as the efficiency of existing priority assignment and routing techniques.
2017
Autores
Maia, C; Nelissen, G; Nogueira, L; Pinho, LM; Perez, DG;
Publicação
2017 IEEE 23RD INTERNATIONAL CONFERENCE ON EMBEDDED AND REAL-TIME COMPUTING SYSTEMS AND APPLICATIONS (RTCSA)
Abstract
Scheduling real-time applications on general purpose multicore platforms is a challenging problem from a timing analysis perspective. Such platforms expose uncontrolled sources of interference whenever concurrent accesses to memory are performed. The non-deterministic bus and memory access behavior complicates the estimations of applications' worst-case execution times (WCET). The 3-phase task model seems a good candidate to circumvent the uncontrolled sources of interference by isolating concurrent memory accesses. A task is divided in three successive phases; first, the task loads its instruction and data in a local memory, then it executes non-preemptively using those pre-loaded instructions and data, and finally, the modified data are pushed back to main memory. Following this execution model, tasks never access the bus during their execution phase. Instead, all the bus accesses are performed during the first and third phases. In this paper, we focus on the global fixed-priority scheduling of the 3-phase task model. A new schedulability test is derived by modelling the interference happening on the bus rather than the interference on the cores as in the state-ot-the-art techniques. The effectiveness of the test is evaluated by comparing it against the state-of-the-art.
2017
Autores
Ali, HI; Akesson, B; Pinho, LM;
Publicação
Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems, SCOPES 2017
Abstract
Future real-time embedded systems will increasingly incorporate mixed application models with timing constraints running on the same multi-core platform. These application models are dataflow applications with timing constraints and traditional real-time applications modelled as independent arbitrary-deadline tasks. These systems require guarantees that all running applications execute satisfying their timing constraints. Also, to be cost-efficient in terms of design, they require efficient mapping strategies that maximize the use of system resources to reduce the overall cost. This work proposes an approach to integrate mixed application models (dataflow and traditional real-time applications) with timing requirements on the same multi-core platform. It comprises three main algorithms: 1) Slack-Based Merging, 2) Timing Parameter Extraction, and 3) Communication-Aware Mapping. Together, these three algorithms play a part in allowing mapping and scheduling of mixed application models in embedded real-time systems. The complete approach and the three algorithms presented have been validated through proofs and experimental evaluation. © 2017 Copyright held by the owner/author(s).
2017
Autores
Maia, C; Yomsi, PM; Nogueira, L; Pinho, LM;
Publicação
EURASIP JOURNAL ON EMBEDDED SYSTEMS
Abstract
This paper extends the work presented in Maia et al. (Semi-partitioned scheduling of fork-join tasks using work-stealing, 2015) where we address the semi-partitioned scheduling of real-time fork-join tasks on multicore platforms. The proposed approach consists of two phases: an offline phase where we adopt a multi-frame task model to perform the task-to-core mapping so as to improve the schedulability and the performance of the system and an online phase where we use the work-stealing algorithm to exploit tasks' parallelism among cores with the aim of improving the system responsiveness. The objective of this work is twofold: (1) to provide an alternative scheduling technique that takes advantage of the semi-partitioned properties to accommodate fork-join tasks that cannot be scheduled in any pure partitioned environment and (2) to reduce the migration overheads which has been shown to be a traditional major source of non-determinism for global scheduling approaches. In this paper, we consider different allocation heuristics and we evaluate the behavior of two of them when they are integrated within our approach. The simulation results show an improvement up to 15% of the proposed heuristic over the state-of-the-art in terms of the average response time per task set.
2017
Autores
Nikolic, B; Pinho, LM;
Publicação
Real-Time Systems
Abstract
2017
Autores
Nikolic, B; Pinho, LM;
Publicação
Real-Time Systems
Abstract
The Network-on-Chip (NoC) architecture is an interconnect network with a good performance and scalability potential. Thus, it comes as no surprise that NoCs are among the most popular interconnect mediums in nowadays available many-core platforms. Over the years, the real-time community has been attempting to make NoCs amenable to the real-time analysis. One such approach advocates to employ virtual channels. Virtual channels are hardware resources that can be used as an infrastructure to facilitate flit-level preemptions between communication traffic flows. This gives the possibility to implement priority-preemptive arbitration policies in routers, which is a promising step towards deriving real-time guarantees for NoC traffic. So far, various aspects of priority-preemptive NoCs were studied, such as arbitration, priority assignment, routing, and workload mapping. Due to a potentially large solution space, the majority of available techniques are heuristic-centric, that is, either pure heuristics, or heuristic-based search strategies are used. Such approaches may lead to an inefficient use of hardware resources, and may cause a resource over-provisioning as well as unnecessarily high design-cost expenses. Motivated by this reality, we take a different approach, and propose an integer linear program to solve the problems of priority assignment and routing of NoC traffic. The proposed method finds optimal routes and priorities, but also allows to reduce the search space (and the computation time) by fixing either priorities or routes, and derive optimal values for remaining parameters. This framework is used to experimentally evaluate both the scalability of the proposed method, as well as the efficiency of existing priority assignment and routing techniques. © 2017 Springer Science+Business Media New York
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