Abstract
In this paper we analyse the estimates of the matrices produced by the non-biased deterministic-stochastic subspace identification algorithms (NBDSSI) proposed by Van Overschee and De Moor ( 1996). First, an alternate expression is derived for the A and C estimates. It is shown that the Chiuso and Picci result ( Chiuso and Picci 2004) stating that the A and C estimates delivered by this algorithm robust version and by the Verhaegen's MOESP (Verhaegen and Dewilde 1992a, Verhaegen and Dewilde 1992b, Verhaegen 1993, Verhaegen 1994) are equal, can be obtained from this expression. An alternative approach for the estimation of matrices B and D in subspace identification is also described. It is shown that the least squares approach for the estimation of these matrices estimation can be just expressed as an orthogonal projection of the future outputs on a lower dimension subspace in the orthogonal complement of the column space of the extended observability matrix. Since this subspace has a dimension equal to the number of outputs, a simpler and numerically more efficient ( but equally accurate) new subspace algorithm is provided.

Abstract
Real-time image processing is a computational intensive task with applications in various engineering fields. In several image processing applications, a significant amount of computing power is committed to image enhancement operations, basic segmentation and identification of regions of interest for further analysis. Such type of front-end processing can be done efficiently by custom data-flow processors closely coupled to an image sensor This paper proposes a visual design environment to support the high-level design of custom data-flow processors for real-time image analysis applications. The tool is embedded in Matlab/Simulink, and the system modeling is done using a library of blocks that implement common low-level image processing operations. Functional validation is performed efficiently by the simulation engine of Simulink in a frame by frame basis, using the functions provided by the image processing toolbox in Matlab. The automatic generation of a synthesizable RTL model guarantees a logic implementation of the system that complies to the high-level model validated, under constraints imposed by the user and the target reconfigurable device.

Abstract
This paper describes the design of a processor specific for testing cores embedded in system-on-chip. This processor which can be implemented within a system's reconfigurable area, shall be responsible for scheduling and control test operations and perform preliminary data processing, as well as to provide the interface with an external tester Building these test operations on-chip allows for simplifying external tester interface and to reduce testing time. The testing procedure and the infrastructure required to test an AID converter is described as an example.

Abstract
This paper addresses the navigation and guidance of an AUV operating in a network of moving acoustic beacons. In this network, the vehicle position is obtained from acoustic signals exchanged between the vehicle and the beacons and is computed in a reference frame associated with the moving beacons. The paper describes the operation of the acoustic network, the mission specification and guidance system that computes the references for the vehicle controllers, and the navigation system that produces all the data required by the guidance system.

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