Engineering
Work description
• Familiarization with the current state of implementation of a tool for converting ONNX models to dataflow graphs (DFGs). • Increase the capabilities of this tool with conversion support for additional ONNX operations (e.g., convolutions), or other optimizations. • Study the state of the art in DFG mappers for hardware accelerators of the Coarse Grained Reconfigurable Array (CGRA) type, and also determine the maturity in the state of the art of mappers based on AI/ML methods. • Test the mappability of the DFGs generated with a state-of-the-art mapper. This component will contribute to a future complete ONNX compilation process for coprocessors.
Academic Qualifications
Enrolment in Licenciatura or MSc in in Informatics Engineering, or similar.
Minimum profile required
Programming experience in C/C++ language
Preference factors
Javascript experience Experience in manipulating data structures in graph format
Application Period
Since 30 Jan 2025 to 12 Feb 2025
Centre
Telecommunications and Multimedia