Informatics, electrical and electronic Engineering
Work description
- Study the state of the art in mapping approaches for CGRA via AI methods and conventional methods. - Familiarizing with existing methods in the working group for converting ONNX models to dataflow graphs (DFGs), compiling via MLIR, and co-simulating RISC-V + CGRA. - Determine the representations for the DFG and CGRA architectural specifications most suitable for use in machine learning methods. - Design and implement a machine learning-based method for mapping DFGs to the target CGRA architecture. - Generation of the configurations resulting from this mapping, and the programs for execution (via simulation) on the final RISC-V + CGRA system. - Collaboration in writing scientific articles to disseminate the results.
Academic Qualifications
Master's degree in electrical engineering, computer science, or related field;
Minimum profile required
- experience in hardware design or heterogeneous systems;- fluent in Portuguese and English (written and spoken)
Preference factors
- RISC-V and/or MLIR experience; - familiarity with ONNX and/or ML / AI frameworks; - fluent in English (written and spoken)
Application Period
Since 19 Dec 2024 to 03 Jan 2025
Centre
Telecommunications and Multimedia