Informatics, Electronics and Digital Systems, Digital Electronics, Microprocessors, Heterogeneous Systems
[Closed]
Work description
- Familiarization with open-source implementations of RISC-V processor-based SoCs. - Familiarization with the existing C/C++-based RISC-V processor codebase, and identification of value-added contributions. - Expansion of the existing core with additional features, mainly an in-house extension for communication with an external accelerator, but also, e.g., instruction extensions for the AI domain or others, or interfaces for communication with accelerators external to the core. - Encapsulate the core as an IP block, to build the SoC via connection to other IP blocks (e.g. buses, memories, UART etc). - Validating the SoC by running basic test programs. - Collaboration in writing a scientific article to disseminate the results.
Academic Qualifications
Graduation or enrollment in a master's degree in electrical engineering, computer science, or a related field;
Minimum profile required
- experience in HDL and FPGAs;- fluent in English (written and spoken).
Preference factors
- RISC-V experience; - experience with Xilinx Vivado/Vitis tools; - fluent in Portuguese and English (written and spoken).
Application Period
Since 06 Dec 2024 to 19 Dec 2024
[Closed]
Centre
Telecommunications and Multimedia